CY28405OC-2 SPECTRALINEAR [SpectraLinear Inc], CY28405OC-2 Datasheet
CY28405OC-2
Related parts for CY28405OC-2
CY28405OC-2 Summary of contents
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Clock Synthesizer with Differential SRC and CPU Outputs Features ® • Supports Intel Pentium 4-type CPUs • Selectable CPU frequencies • 3.3V power supply • Nine copies of PCI clocks • Four copies of 3V66 with one optional VCH • ...
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Pin Description Pin No. Name 1 FS_A/REF_0 2 FS_B/REF_1 4 XIN 5 XOUT 39, 42, CPUT(0:1), 38, 41, CPUC(0:1), 45, 44 CPUT_ITP, CPUC_ITP 36, 35 SRCT, SRCC 26, 29, 30 3V66(2:0) 25 3V66_3/VCH PCI_F(0:2) 12, 13, 14, ...
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Table 1. Frequency Select Table (FS_A FS_B) FS_A FS_B CPU 0 0 100 MHz 0 B6b7 REF 200 MHz 1 0 133 MHz 1 B6b7 Hi-Z Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte ...
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Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description .... Data Byte (N–1) –8 bits .... Acknowledge from slave .... Data Byte N –8 bits .... Acknowledge from slave .... Stop Table 5. Byte Read ...
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Byte 1: Control Register Bit @Pup 7 0 SRCT SRCC 6 1 SRCT SRCC 5 1 Reserved 4 1 Reserved 3 1 Reserved 2 1 CPUT_ITP, CPUC_ITP 1 1 CPUT1, CPUC1 0 1 CPUT0, CPUC0 Byte 2: Control Register Bit ...
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Byte 4: Control Register Bit @Pup 7 0 USB_48 6 1 USB_48 5 0 PCIF2 4 0 PCIF1 3 0 PCIF0 2 1 PCIF2 1 1 PCIF1 0 1 PCIF0 Byte 5: Control Register Bit @Pup 7 1 DOT_48 6 ...
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Byte 6: Control Register (continued) Bit @Pup 2 0 PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP 1 1 REF_1 0 1 REF_0 Byte 7: Control Register Bit @Pup 7 0 Revision ID Bit Revision ID Bit ...
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Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with ...
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PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 ...
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FS_A, FS_B VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD_A = 2.0V S0 Power Off Figure 6. Clock Generator Power-up/Run State Diagram Absolute Maximum Conditions Parameter Description V Core Supply ...
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Absolute Maximum Conditions Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description 3.3 Operating Voltage DD DDA V ...
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AC Electrical Specifications Parameter Description T Any CPUT/C to CPUT/C Clock Skew SKEW T CPUT/C Cycle to Cycle Jitter CCJ CPUT and CPUC Rise and Fall Times Rise/Fall Matching RFM T Rise Time Variation ...
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AC Electrical Specifications Parameter Description T PCI Duty Cycle DC T Spread Disabled PCIF/PCI Period PERIOD T Spread Enabled PCIF/PCI Period PERIOD T PCIF and PCI High Time HIGH T PCIF and PCI Low Time LOW PCIF ...
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Table 7. Group Timing Relationship and Tolerances Group 3V66 to PCI Table 8. USB to DOT Phase Offset Parameter Typical DOT Skew 0° USB Skew 180° VCH SKew 0° Test and Measurement Set-up Table 9. Maximum Lumped Capacitive Output Loads ...
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Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement) Table 10.CPU Clock Current Select Function Board Target Trace/Term Z 50 Ohms Rev 1.0, November 22, 2006 3 .3 ...
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... Ordering Information Part Number CY28405OC-2 48-pin SSOP CY28405OC-2T 48-pin SSOP – Tape and Reel Package Drawing and Dimensions While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in ...
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Clock Synthesizer with Differential SRC and CPU Outputs Features ® • Supports Intel Pentium 4-type CPUs • Selectable CPU frequencies • 3.3V power supply • Nine copies of PCI clocks • Four copies of 3V66 with one optional VCH • ...
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Pin Description Pin No. Name 1 FS_A/REF_0 2 FS_B/REF_1 4 XIN 5 XOUT 39, 42, CPUT(0:1), 38, 41, CPUC(0:1), 45, 44 CPUT_ITP, CPUC_ITP 36, 35 SRCT, SRCC 26, 29, 30 3V66(2:0) 25 3V66_3/VCH PCI_F(0:2) 12, 13, 14, ...
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Table 1. Frequency Select Table (FS_A FS_B) FS_A FS_B CPU 0 0 100 MHz 0 B6b7 REF 200 MHz 1 0 133 MHz 1 B6b7 Hi-Z Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte ...
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Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description .... Data Byte (N–1) –8 bits .... Acknowledge from slave .... Data Byte N –8 bits .... Acknowledge from slave .... Stop Table 5. Byte Read ...
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Byte 1: Control Register Bit @Pup 7 0 SRCT SRCC 6 1 SRCT SRCC 5 1 Reserved 4 1 Reserved 3 1 Reserved 2 1 CPUT_ITP, CPUC_ITP 1 1 CPUT1, CPUC1 0 1 CPUT0, CPUC0 Byte 2: Control Register Bit ...
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Byte 4: Control Register Bit @Pup 7 0 USB_48 6 1 USB_48 5 0 PCIF2 4 0 PCIF1 3 0 PCIF0 2 1 PCIF2 1 1 PCIF1 0 1 PCIF0 Byte 5: Control Register Bit @Pup 7 1 DOT_48 6 ...
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Byte 6: Control Register (continued) Bit @Pup 2 0 PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP 1 1 REF_1 0 1 REF_0 Byte 7: Control Register Bit @Pup 7 0 Revision ID Bit Revision ID Bit ...
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Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with ...
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PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 ...
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FS_A, FS_B VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD_A = 2.0V S0 Power Off Figure 6. Clock Generator Power-up/Run State Diagram Absolute Maximum Conditions Parameter Description V Core Supply ...
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Absolute Maximum Conditions Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description 3.3 Operating Voltage DD DDA V ...
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AC Electrical Specifications Parameter Description T Any CPUT/C to CPUT/C Clock Skew SKEW T CPUT/C Cycle to Cycle Jitter CCJ CPUT and CPUC Rise and Fall Times Rise/Fall Matching RFM T Rise Time Variation ...
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AC Electrical Specifications Parameter Description T PCI Duty Cycle DC T Spread Disabled PCIF/PCI Period PERIOD T Spread Enabled PCIF/PCI Period PERIOD T PCIF and PCI High Time HIGH T PCIF and PCI Low Time LOW PCIF ...
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Table 7. Group Timing Relationship and Tolerances Group 3V66 to PCI Table 8. USB to DOT Phase Offset Parameter Typical DOT Skew 0° USB Skew 180° VCH SKew 0° Test and Measurement Set-up Table 9. Maximum Lumped Capacitive Output Loads ...
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Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement) Table 10.CPU Clock Current Select Function Board Target Trace/Term Z 50 Ohms Rev 1.0, November 22, 2006 3 .3 ...
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... Ordering Information Part Number CY28405OC-2 48-pin SSOP CY28405OC-2T 48-pin SSOP – Tape and Reel Package Drawing and Dimensions While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in ...
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Clock Synthesizer with Differential SRC and CPU Outputs Features ® • Supports Intel Pentium 4-type CPUs • Selectable CPU frequencies • 3.3V power supply • Nine copies of PCI clocks • Four copies of 3V66 with one optional VCH • ...
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Pin Description Pin No. Name 1 FS_A/REF_0 2 FS_B/REF_1 4 XIN 5 XOUT 39, 42, CPUT(0:1), 38, 41, CPUC(0:1), 45, 44 CPUT_ITP, CPUC_ITP 36, 35 SRCT, SRCC 26, 29, 30 3V66(2:0) 25 3V66_3/VCH PCI_F(0:2) 12, 13, 14, ...
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Table 1. Frequency Select Table (FS_A FS_B) FS_A FS_B CPU 0 0 100 MHz 0 B6b7 REF 200 MHz 1 0 133 MHz 1 B6b7 Hi-Z Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte ...
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Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description .... Data Byte (N–1) –8 bits .... Acknowledge from slave .... Data Byte N –8 bits .... Acknowledge from slave .... Stop Table 5. Byte Read ...
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Byte 1: Control Register Bit @Pup 7 0 SRCT SRCC 6 1 SRCT SRCC 5 1 Reserved 4 1 Reserved 3 1 Reserved 2 1 CPUT_ITP, CPUC_ITP 1 1 CPUT1, CPUC1 0 1 CPUT0, CPUC0 Byte 2: Control Register Bit ...
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Byte 4: Control Register Bit @Pup 7 0 USB_48 6 1 USB_48 5 0 PCIF2 4 0 PCIF1 3 0 PCIF0 2 1 PCIF2 1 1 PCIF1 0 1 PCIF0 Byte 5: Control Register Bit @Pup 7 1 DOT_48 6 ...
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Byte 6: Control Register (continued) Bit @Pup 2 0 PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP 1 1 REF_1 0 1 REF_0 Byte 7: Control Register Bit @Pup 7 0 Revision ID Bit Revision ID Bit ...
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Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with ...
Page 41
PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 ...
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FS_A, FS_B VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD_A = 2.0V S0 Power Off Figure 6. Clock Generator Power-up/Run State Diagram Absolute Maximum Conditions Parameter Description V Core Supply ...
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Absolute Maximum Conditions Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description 3.3 Operating Voltage DD DDA V ...
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AC Electrical Specifications Parameter Description T Any CPUT/C to CPUT/C Clock Skew SKEW T CPUT/C Cycle to Cycle Jitter CCJ CPUT and CPUC Rise and Fall Times Rise/Fall Matching RFM T Rise Time Variation ...
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AC Electrical Specifications Parameter Description T PCI Duty Cycle DC T Spread Disabled PCIF/PCI Period PERIOD T Spread Enabled PCIF/PCI Period PERIOD T PCIF and PCI High Time HIGH T PCIF and PCI Low Time LOW PCIF ...
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Table 7. Group Timing Relationship and Tolerances Group 3V66 to PCI Table 8. USB to DOT Phase Offset Parameter Typical DOT Skew 0° USB Skew 180° VCH SKew 0° Test and Measurement Set-up Table 9. Maximum Lumped Capacitive Output Loads ...
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Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement) Table 10.CPU Clock Current Select Function Board Target Trace/Term Z 50 Ohms Rev 1.0, November 22, 2006 3 .3 ...
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... Ordering Information Part Number CY28405OC-2 48-pin SSOP CY28405OC-2T 48-pin SSOP – Tape and Reel Package Drawing and Dimensions While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in ...