CY28312B-2T SPECTRALINEAR [SpectraLinear Inc], CY28312B-2T Datasheet
CY28312B-2T
Related parts for CY28312B-2T
CY28312B-2T Summary of contents
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... VDD_REF REF2 REF1/FS1* REF0/FS0* VDD_CPU *FS3/24_48MHz CPUT0,CPUC0 2 CPUT_CS,CPUC_CS *SEL24_48#/PCI0 VDD_AGP AGP0:2 3 VDD_PCI PCI0/SEL24_48#* PCI1:8 5 PCI9_E RST# VDD_48MHz 48MHz/FS3* 24_48MHz/FS4* Tel:(408) 855-0555 Fax:(408) 855-0550 CY28312B-2 [1] VDD_REF 1 48 REF0/FS0* GND_REF 47 REF1/FS1 REF2 X2 45 REF_STOP#* 4 VDD_48MHz 5 44 AGP_STOP#* *FS2/48MHz 43 ...
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... AGP STOP Input. This input will disable AGP0:2 when it is active. I REF STOP Input. This input will disable REF0:2, 24_48MHz and 48 MHz outputs when it is active. I Power-down Input. This input will trigger the clock generator into Power-down mode when it is active. CY28312B-2 Pin Description Page ...
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... GND_PCI, GND_AGP, GND_Core, GND_CPU Serial Data Interface The CY28312B-2 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word write, byte/word read, block write and block read operations from the ...
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... Slave address – 7 bits 9 Write 10 Acknowledge from slave 11:18 Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits 28 Read CY28312B-2 Page ...
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... Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Description CY28312B-2 Serial Configuration Map The serial bits will be read by the clock driver in the following order: Byte 0–Bits Byte 1–Bits Byte N–Bits ...
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... X Latched FS0 input X Reserved 0 Reserved 0 SEL4 0 Default 1 Reserved 1 Reserved 1 Reserved 1 Reserved CY28312B-2 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) Description (Active/Inactive) (Active/Inactive) Reserved (Active/Inactive) (Active/Inactive) Reserved (Active/Inactive) (Active/Inactive) Description Reserved 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings These bits store the time-out value of the Watchdog timer ...
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... Watchdog Timer Time-out Status bit time-out occurs (READ); Ignore (WRITE time-out occurred (READ); Clear WD_TO_STATUS (WRITE Stop and reload Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. 0 Reserved CY28312B-2 Description Description Description Description Page ...
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... CPU output frequency.when a Watchdog timer time-out occurs 0 The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, CY28312B-2 will use the same 0 frequency ratio stated in the Latched FS[4:0] register. When it is set, 0 CY28312B-2 will use the frequency ratio stated in the SEL[4:0] register. ...
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... The setting of FS_Override bit determines the frequency ratio for CPU, 0 SDRAM, AGP and SDRAM. When it is cleared, CY28312B-2 will use the same 0 frequency ratio stated in the Latched FS[4:0] register. When it is set, 0 CY28312B-2 will use the frequency ratio stated in the SEL[4:0] register. ...
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... Reserved 1 0 Reserved 1 1 200 190 180 170 150 140 120 110 66 200 166 100 133.3 CY28312B-2 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Output Frequency 3V66 PCI 78.0 39.0 77.0 38.5 76.0 38.0 73.5 36.8 72.0 36.0 71.0 35.5 69.0 34.5 68.0 34.0 62.0 31.0 61.0 30.5 78.0 39.0 76.7 38.3 75.3 37.7 72.0 36.0 70.0 35.0 68.0 34 ...
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... Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All of the related registers are summarized inTable 6. Description CY28312B-2 Page ...
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... M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Fixed Value for Range of N-Value Register M-Value Register for Different CPU Frequency 93 48 CY28312B-2 97–255 127–245 Page ...
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... All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 4. The CY28312B-2 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. ...
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... Average value during switching transition. Used for determining series termination value. Test Condition/Comments Measured from 0.8V to 2.0V Measured from 2.0V to 0.8V Measured at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. CY28312B-2 Min. Typ. Max CPU = 100 MHz CPU = 133 MHz Min. Typ. Max. ...
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... Measured from 0.8V to 2.0V Measured from 2.0V to 0.8V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. CY28312B-2 Min. Typ. Max. Unit 300 ps 3 ...
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... CPUCLK_T Clock Chip CPUDriver CPUCLK_C Ordering Information Ordering Code CY28312B-2 48-pin SSOP CY28312B-2T 48-pin SSOP–Tape and Reel Rev 1.0, November 21, 2006 VDD + V1 3 Length = 5” Length = 5” Figure 1. K7 Open Drain Clock Driver Test Circuit Package Type CY28312B-2 1 ...
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... Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 21, 2006 48-Lead Shrunk Small Outline Package O48 CY28312B-2 Page ...