CY28439 SpectraLinear, CY28439 Datasheet
CY28439
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CY28439 Summary of contents
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... SRCT (PCI Ex) SRCC (PCI Ex) VDD_SRC SRCT4_SATA SRCC4_SATA VDD_48Mhz DOT96T DOT96C VDD_48 USB48 VDD_48 24/48 VDD_PCI PCI VDD_PCI PCIF Watchdog SRESET# Timer Tel:(408) 855-0555 www.DataSheet4U.com CY28439 PCI REF DOT96 USB VSS_PCI 2 55 PCI3 *FS_E/PCI4 3 54 PCI5 4 53 ...
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... CPU frequency selection/Reference clock. PD Selects test mode if pulled to V Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifica- tions. This output is open drain type with a high (>100-k ) internal pull-up resistor. www.DataSheet4U.com Description when VTT_PWRGD# is asserted low. IHFS_C CY28439 Page ...
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... Tristate Tristate Tristate Tristate Tristate REF/N REF/N REF/N REF/N REF/N Figure 1. CPU and SRC Frequency Select Tables www.DataSheet4U.com CY28439 CPU N SRC PLL SRC M SRC N SRC N allowable Gear divider (not DEFAULT allowable range for Constants changeable range for DAF ...
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... Byte Read Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop www.DataSheet4U.com CY28439 Page ...
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... PCI4 Output Enable 0 = Disabled Enabled PCI3 PCI3 Output Enable 0 = Disabled Enabled PCI2 PCI2 Output Enable 0 = Disabled Enabled PCI1 PCI1 Output Enable 0 = Disabled Enabled PCI0 PCI0 Output Enable 0 = Disabled Enabled PCIF2 PCIF2 Output Enable 0 = Disabled Enabled www.DataSheet4U.com CY28439 Description Description Description Page ...
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... RESERVED, Set = 0 SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted RESERVED, Set = 0 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted www.DataSheet4U.com CY28439 Description Description Description Description Page ...
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... SRC Spread Spectrum Enable 0 = Spread off Spread on SRC_SS Spread Selection for SRC PLL 0: –0.5% (peak to peak) 1: –1.0% (peak to peak) RESERVED, Set = 0 USB USB 48-MHz Output Drive Strength PCI 33-MHz Output Drive Strength RESERVED www.DataSheet4U.com CY28439 Description Description Description Page ...
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... The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used. www.DataSheet4U.com CY28439 Description Description Description Page ...
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... Select SRC_PLL. RESERVED, Set = 0 RESERVED, Set = 0 PCIF Free running 33-MHz Output Drive Strength Watchdog Recovery Bit Name Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit www.DataSheet4U.com CY28439 Description Description Description Description Page ...
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... Watchdog Autorecovery Watchdog Autorecovery Mode The CY28439 requires a Parallel Resonance Crystal. Substi- tuting a series resonance crystal will cause the CY28439 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading ...
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... This mode allows the user to select the CPU output frequencies using the Software Frequency select bits in the SMBUS register. FSEL—There will be four bits (for 16 combinations) to select predetermined CPU frequencies from a table. The table selec- tions are detailed in section Figure 1. www.DataSheet4U.com CY28439 Page ...
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... When this recovery mode is selected, in the event of a Watchdog timeout, the M and N values stored in the Recovery M and N registers should be reloaded. The current values of M and N will be latched into the internal recovery M and N registers by the WD_EN bit being set. www.DataSheet4U.com CY28439 Page ...
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... PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure example showing the relationship of clocks coming up. Figure 4. Power-down Assertion Timing Waveform www.DataSheet4U.com CY28439 Page ...
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... Delay VTT_PW RGD# State 1 On Figure 6. VTT_PWRGD# Timing Diagram S1 VTT_PW RGD# = Low Delay >0.25 ms VDD_A = off Norm al Operation VTT_PW RGD# = toggle www.DataSheet4U.com Device is not affected, VTT_PW RGD# is ignored State 2 State Sample Inputs straps W ait for <1.8ms S3 Enable Outputs CY28439 Page ...
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... SDATA, SCLK SDATA, SCLK Except internal pull-up resistors, 0 < V Except internal pull-down resistors, 0 < – max. load and freq. per Figure 10 PD asserted, Outputs Driven PD asserted, Outputs Tri-state www.DataSheet4U.com CY28439 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD – ...
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... Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX www.DataSheet4U.com CY28439 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 – 500 ps – ...
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... Determined as a fraction of 2*(T – T )/( Math averages Figure 10 Math averages Figure 10 See Figure 10. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V www.DataSheet4U.com CY28439 Min. – OX – = 0.175 0.525V 130 OH – – – 660 –150 250 – V – ...
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... Measured at 1.5V using frequency counter over 0.15s Measurement at 2.0V Measurement at 0.8V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measurement taken@1.5V waveform Measurement taken from cross point www.DataSheet4U.com CY28439 Min. – – 10.41354 10.41979 OX 10.16354 10.66979 OX – OX – ...
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... asurem ent P oint easu rem ent P oint easu rem ent P oint easu rem ent P oint easu rem ent P oint CY28439 Max. Unit 700 ps 700 69.8622 ns 70.86224 ns 4.0 V/ns 4.0 V/ns 1000 ps 1 ...
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... Package Type www.DataSheet4U.com Product Flow Commercial Commercial Commercial Commercial CY28439 Page ...
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... MAX. 0.20[0.008] 0.051[0.002] 0.152[0.006] 0.170[0.006] SEATING 0.279[0.011] PLANE www.DataSheet4U.com CY28439 DIMENSIONS IN INCHES MIN. MAX. 0.005 .010 0.010 0.024 0.040 0°-8° DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG ...