CY28412 SpectraLinear, CY28412 Datasheet - Page 6

• Manufacturer Part Number: CY28412
• Description: Clock Generator
• Manufacturer: SpectraLinear

Rev 1.0, November 20, 2006
Byte 3: Control Register 3 (continued)
Byte 4: Control Register 4
Byte 5: Control Register 5
Bit
Bit
Bit
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
SRC[T/C][6:0],SATA[T/C] SRC[T/C], SATA[T/C]Stop Drive Mode
SRC[T/C][6:0],SATA[T/C] SRC[T/C], SATA[T/C] PWRDWN Drive Mode
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DOT96[T/C]
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
PCIF1
PCIF0
Name
Name
Name
SRC2
SRC1
SRC0
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]0 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
RESERVED, Set = 0
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
RESERVED, Set = 0
RESERVED, Set = 1
RESERVED, Set = 1
RESERVED, Set = 1
0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP#
asserted
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED, Set = 0
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Description
Description
Description
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CY28412
Page 6 of 16