CY28412 SpectraLinear, CY28412 Datasheet
CY28412
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CY28412 Summary of contents
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... CPU(T/C)2_ITP] VDD_SRC SRCT[0:6], SRCC[0:6], SATA[T/C] VDD_PCI TEST_SEL/PCIF0 PCI[0:5] ITP_EN/PCIF1 VDD_PCIF PCIF[0:1] USB48/FS_B VDD_48 MHz DOT96T DOT96C VTT_PwrGd#/PD USB_48 VDD_SRC GND_SRC Tel:(408) 855-0555 www.DataSheet4U.com CY28412 ® Grantsdale Chipset SRC PCI REF PCI0 1 56 PCI1 2 55 VDD_PCI 3 54 GND_PCI 4 ...
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... LVTTL input is a level sensitive strobe used to latch the REF0/FSC, REF1/FSA, USB48/FSB, TEST_SEL/PCIF0 and ITP_EN/PCIF1 inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a realtime input for asserting power-down (active HIGH). I 14.318-MHz crystal input 14.318-MHz crystal output. www.DataSheet4U.com CY28412 Description Page ...
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... MHz 33 MHz 100 MHz 33 MHz Description Bit 1 2 11: 21: 30:37 38 www.DataSheet4U.com CY28412 REF0 DOT96 14.318 MHz 96 MHz 14.318 MHz 96 MHz 14.318 MHz 96 MHz 14.318 MHz 96 MHz 14.318 MHz 96 MHz 14.318 MHz 96 MHz 14.318 MHz 96 MHz 14.318 MHz 96 MHz Block Read Protocol ...
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... SRC[T/C]2 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z Enable www.DataSheet4U.com CY28412 Block Read Protocol Description Data byte from slave – 8 bits Acknowledge from master Data byte from slave – 8 bits Acknowledge from master Data byte N from slave – 8 bits ...
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... Free-running Stopped with SW PCI_STP# Allow control of SRC[T/C]4 with assertion of SW PCI_STP Free-running Stopped with SW PCI_STP# Allow control of SRC[T/C]3with assertion of SW PCI_STP Free-running Stopped with SW PCI_STP# Allow control of SATA[T/C] with assertion of SW PCI_STP Free-running Stopped with SW PCI_STP# www.DataSheet4U.com CY28412 Description Description Description Page ...
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... RESERVED, Set = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted www.DataSheet4U.com CY28412 Description Description Description Page ...
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... Crystal Recommendations The CY28412 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28412 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU 1 ) Ce2 + Cs2 + Ci2 frequencies 100,133,166,200,266,333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 VTT_PWRGD#. www.DataSheet4U.com CY28412 s after asserting Page ...
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... After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of each other. Clock Chip Ci2 Ci1 X2 X1 Cs1 XTAL Ce1 Ce2 Figure 2. Crystal Loading Example Figure 3. Power-down Assertion Timing Waveform www.DataSheet4U.com CY28412 Pin Cs2 Trace 2.8pF Trim 33pF Page ...
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... State 1 State 2 On Figure 5. VTT_PWRGD# Timing Diagram S1 VTT_PW Low D elay >0.25m orm al VD D_A = off O peration VTT_PW toggle www.DataSheet4U.com CY28412 Device is not affected, VTT_PW RGD# is ignored State ple Inputs straps W ait for <1.8m s Enable O utputs Page ...
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... SDATA, SCLK SDATA, SCLK except internal pull-up resistors, 0 < V except internal pull-down resistors, 0 < – max load and freq per Figure 8 PD asserted, Outputs driven PD asserted, Outputs Hi-Z www.DataSheet4U.com CY28412 Min. Max. –0.5 4.6 –0.5 4.6 –0 0.5 VDC DD –65 150 ...
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... Measured at crossing point V OX Measured from V = 0.175 Determined as a fraction of 2*(T – Math averages Figure 8 Math averages Figure 8 See Figure 8. Measure SE Measured at crossing point V OX Measured at crossing point www.DataSheet4U.com CY28412 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 – 500 ps – 300 ...
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... OX – OX – 0.175 0.525V OH 175 – T )/( – – – 660 –150 250 – –0.3 – 45 20.8271 8.094 7.694 CY28412 Max. Unit 125 ps 300 ppm 700 125 ps 125 ps 850 mv – mv 550 HIGH V 0.3 – V 0.2 V 250 ...
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... PCI, USB, and REF output signals. PCI/ USB REF Rev 1.0, November 20, 2006 (continued) Condition Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Figure 7. Single-ended Load Configuration www.DataSheet4U.com CY28412 Min. Max. 1.0 2.0 – 350 45 55 69.8203 69.8622 0.5 2.0 – 1000 – ...
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... Figure 8. 0.7V Single-ended Load Configuration www.DataSheet4U.com CY28412 Page ...
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... Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 20, 2006 Package Type 56-lead Shrunk Small Outline Package O56 www.DataSheet4U.com CY28412 Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C ...