CY28412 SpectraLinear, CY28412 Datasheet - Page 3

• Manufacturer Part Number: CY28412
• Description: Clock Generator
• Manufacturer: SpectraLinear

Rev 1.0, November 20, 2006
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B and FS_C input values. For all logic
levels of FS_A, FS_B and FS_C VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B and FS_C transitions will be ignored, except in
test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
Table 1. Frequency Select Table (FS_A, FS_B, FS_C)
Table 2. Command Code Definition
Table 3. Block Read and Block Write Protocol
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
FS_C
Bit
7
20:27
29:36
38:45
11:18
1
0
0
0
0
1
1
1
Bit
2:8
10
19
28
37
46
1
9
0 = Block read or block write operation, 1 = Byte read or byte write operation
FS_B
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
0
0
1
1
0
0
1
1
Block Write Protocol
FS_A
1
1
1
0
0
0
0
1
Description
Reserved
100 MHz
133 MHz
166 MHz
200 MHz
266 MHz
333 MHz
400 MHz
CPU
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
SRC
Description
PCIF/PCI
izes to their default setting upon power-up, and therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for pow-
er management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
21:27
30:37
11:18
Bit
2:8
10
19
20
28
29
38
1
9
Start
Slave address – 7 bits
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Slave address – 7 bits
Read = 1
Acknowledge from slave
Acknowledge from master
Write = 0
Repeat start
Byte count from slave – 8 bits
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
REF0
Block Read Protocol
Description
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
DOT96
www.DataSheet4U.com
CY28412
Page 3 of 16
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
USB