LMX1600SLB National Semiconductor, LMX1600SLB Datasheet - Page 9

• Manufacturer Part Number: LMX1600SLB
• Description: PLLatinum Low Cost Dual Frequency Synthesizer
• Manufacturer: National Semiconductor

2.0 Programming Description
1.1 GHz option (12 bit)
Note 14: Divide ratio: 3 to 4,095 (Divide ratios less than 3 are prohibited)
2.3.7 Pulse Swallow Function
The N divider counts such that it divides the VCO RF frequency by (P+1) for A times, and then divides by P for (B – A ) times.
The B value (B_CNTR) must be
option, from 240 to 65,535 for 1.1 GHz option, and from 56 to 32,767 for 500 MHz option. Divider ratios less than the minimum
value are achievable as long as the binary counter value is greater than or equal to the swallow counter value (B_CNTR
A_CNTR).
f
N = (P x B) + A
2.4 CHARGE PUMP CONTROL WORD (CP_WORD)
AUX_CP_GAIN (MAIN_R[17]) and MAIN_CP_GAIN (MAIN_R[16]) are used to select charge pump current magnitude either low
gain mode (160 µA typ) or high gain mode (1600 µA typ)
AUX_ PD_POL (MAIN_R[15]) and MAIN_ PD_POL (MAIN_R[14]) are respectively set to one when Aux or Main VCO character-
istics are positive as in (1) below. When VCO frequency decreases with increasing control voltage (2) PD_POL should set to zero.
VCO
Divide Ratio
f
f
R:
N:
B:
A:
P:
MSB
VCO
OSC
MAIN_CP_GAIN
4,095
AUX_CP_GAIN
AUX_CP_GAIN
MAIN_PD_POL
= N x ( f
AUX_PD_POL
3
4
:
:
•
MAIN_B_CNTR
See section 2.3.7 for calculation of VCO output frequency.
Output frequency of external voltage controlled oscillator (VCO)
Output frequency of the external reference frequency oscillator (input to OSC
Preset divide ratio of binary programmable reference counter (R_CNTR)
Preset divide ratio of main programmable integer N counter (N_CNTR)
Preset divide ratio of binary programmable B counter (B_CNTR)
Preset value of binary 4-bit swallow A counter (A _CNTR)
Preset modulus of dual modulus prescaler (P = 32 for 2 GHz option, P=16 for 1.1 GHz option, and P=8 for 500 MHz
option)
BIT
OSC
11
0
0
1
•
/ R )
MAIN_A_CNTR.
10
0
0
1
•
MAIN_CP_GAIN
MAIN_R[17]
MAIN_R[16]
MAIN_R[15]
MAIN_R[14]
9
0
0
1
LOCATION
•
MAIN_B_CNTR
8
0
0
1
3. The continuous divider range for the Main PLL N divider is from 992 to 65,535 for 2 GHz
•
7
0
0
1
•
Aux Charge Pump Current Gain
Main Charge Pump Current Gain
Aux Phase Detector Polarity
Main Phase Detector Polarity
6
0
0
1
•
AUX_PD_POL
5
0
0
1
•
(Continued)
4
0
0
1
•
FUNCTION
9
3
0
0
1
•
2
0
1
1
•
MAIN_PD_POL
1
1
0
1
•
0
1
0
1
•
LSB
IN
).
Negative
Negative
LOW
LOW
0
www.national.com
Positive
Positive
HIGH
HIGH
1