LMX1600SLB National Semiconductor, LMX1600SLB Datasheet
LMX1600SLB
Related parts for LMX1600SLB
LMX1600SLB Summary of contents
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... LMX1600 or LMX1602. Powerdown for the PLL is hardware controlled. The LMX1600/01/02 is available pin TSSOP surface mount plastic package. Functional Block Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. MICROWIRE ™ and PLLatinum ™ are trademarks of National Semiconductor Corporation. © 1998 National Semiconductor Corporation ...
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Connection Diagram Order Number LMX1600TM, LMX1601TM, or LMX1602TM Pin Description Pin Pin Name I/O No. 1 FoLD O Multiplexed output of the Main/Aux programmable or reference dividers and Main/Aux lock detect. CMOS output. (See Programming Description 2.5) 2 OSC I ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Power Supply Voltage Voltage on any pin with GND=0V Storage Temperature Range Lead Temp. (solder 4 sec) ESD-Human Body Model (Note 2) Recommended Operating Conditions ...
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Electrical Characteristics ( 3.0V 25˚C except as specified) CC MAIN CC AUX A Symbol Parameter DIGITAL INTERFACE (DATA, CLK, LE, EN, FoLD) I High-Level Input Current IH I Low-Level Input Current IL I OSC Input ...
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... Functional Description The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthe- sizer such as the National Semiconductor LMX1600/01/02, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, cur- rent mode charge pump, as well as programmable reference [R], and feedback [N] frequency dividers ...
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Functional Description the phase detector inputs is less than 15 ns for 4 consecutive comparison cycles. The lock detect output is low when the error between the phase detector outputs is more than 30 ns for one comparison cycle. ...
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Programming Description 2.2.2 MAIN_R REGISTER If the Control Bits (CTL [1:0]) are 1 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which sets the Main PLL 12-bit R counter divide ratio ...
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Programming Description 2.3.4 MAIN_N Register If the Control Bits (CTL[1:0]) are 1 1 when LE transitions high, data is transferred from the 18-bit shift register into the MAIN_N register latch which sets 16-bit programmable N divider value. The Main ...
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Programming Description 1.1 GHz option (12 bit) MAIN_B_CNTR Divide Ratio • • • • • • 4,095 ...
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Programming Description 2.4.1 VCO Characteristics 2.4.2 Phase Comparator and Internal Charge Pump Characteristics (AUX_PD_POL/MAIN_PD_POL = 1) Note 15 phase detector input from reference counter phase detector input from programmable N counter. Phase difference detection range: ...
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Programming Description 2.5.1 Lock Detect Digital Filter The Lock Detect Digital Filter compares the difference between the phase of the inputs of the phase detector generated delay of approximately 15 ns. To enter the locked state ...
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Programming Description 2.5.3 OSC Mode Programming The OSC pin can be optimized for operating with an external crystal resonator or an external reference frequency source (i.e. out TCXO). If the application uses an external reference frequency source, the current ...
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Programming Description 2.7 TYPICAL APPLICATION EXAMPLE OPERATIONAL NOTES: * VCO is assumed AC coupled increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10 IN 200 depending ...
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