LMX1600SLB National Semiconductor, LMX1600SLB Datasheet - Page 8

• Manufacturer Part Number: LMX1600SLB
• Description: PLLatinum Low Cost Dual Frequency Synthesizer
• Manufacturer: National Semiconductor

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2.0 Programming Description
2.3.4 MAIN_N Register
If the Control Bits (CTL[1:0]) are 1 1 when LE transitions high, data is transferred from the 18-bit shift register into the MAIN_N
register latch which sets 16-bit programmable N divider value. The Main N divider is a 16-bit counter which is fully programmable
from 992 to 65,535 for 2 GHz option and from 240 to 65,535 for 1.1 GHz option. The MAIN_N register consists of the 5-bit (2 GHz
option) or 4-bit (1.1 GHz option) swallow counter (MAIN_A_CNTR) and the 11-bit (2 GHz option) or 12-bit (1.1 GHz option) pro-
grammable counter (MAIN_B_CNTR). Serial data format for the MAIN_N register latch shown below. The divide ratio must be
992 (2 GHz option) or 240 (1.1 GHz option) for a continuous divide range. The divide ratio is programmed using the bits
MAIN _A_CNTR and MAIN_B_CNTR as shown in tables 2.3.5 and 2.3.6 The pulse swallow function which determines the divide
ratio is described in Section 2.3.7.
2 GHz option
1.1 GHz option
2.3.5 Swallow Counter Divide Ratio (Main A COUNTER)
2 GHz option (5 bit)
Note 11: Swallow Counter Value: 0 to 31
2.3.6 Programmable Counter Divide Ratio (Main B COUNTER)
2 GHz option (11 bit)
Note 13: Divide ratio: 3 to 2,047 (Divide ratios less than 3 are prohibited)
Divide Ratio
Swallow
2,047
Count
MAIN_N
MAIN_N
(A)
3
4
31
•
0
1
•
MAIN_B_CNTR
See section 2.3.7 for calculation of VCO output frequency.
10
0
0
1
•
First Bit
First Bit
17
17
4
0
0
1
•
MAIN_A_CNTR.
9
0
0
1
•
MAIN_A_CNTR
16
16
3
0
0
1
•
8
0
0
1
•
15
15
2
0
0
1
•
MAIN_B_CNTR
7
0
0
1
•
14
14
1
0
0
1
•
AUX_B_CNTR[10:0]
6
0
0
1
•
AUX_B_CNTR[11:0]
13
13
0
0
1
1
•
5
0
0
1
•
12
12
SHIFT REGISTER BIT LOCATION
SHIFT REGISTER BIT LOCATION
4
0
0
1
•
(Continued)
11
11
3
0
0
1
•
10
10
8
2
0
1
1
•
9
9
1.1 GHz option (4 bit)
Note 12: Swallow Counter Value: 0 to 15
1
1
0
1
•
Swallow
8
8
Count
(A)
15
0
1
•
0
1
0
1
•
7
7
6
6
AUX_A_CNTR[4:0]
3
0
0
1
•
MAIN_A_CNTR
AUX_A_CNTR[3:0]
5
5
2
0
0
1
•
4
4
1
0
0
1
•
3
3
0
0
1
1
•
2
2
Last Bit
Last Bit
1
1
1
1
0
1
0
1