LMX1600SLB National Semiconductor, LMX1600SLB Datasheet - Page 6

• Manufacturer Part Number: LMX1600SLB
• Description: PLLatinum Low Cost Dual Frequency Synthesizer
• Manufacturer: National Semiconductor

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1.0 Functional Description
the phase detector inputs is less than 15 ns for 4 consecutive
comparison cycles. The lock detect output is low when the
error between the phase detector outputs is more than 30 ns
for one comparison cycle. The lock detect output is always
low when the PLL is in power down mode. For further de-
scription see Programming Description 2.5.
2.0 Programming Description
2.1 MICROWIRE INTERFACE
The descriptions below detail the 18-bit data register loaded through the MICROWIRE Interface. The 18-bit shift register is used
to program the 12-bit Main and Aux R counter registers and the 16-bit Main and Aux N counter registers. The shift register con-
sists of a 16-bit DATA field and a 2-bit control (CTL [1:0]) field as shown below. The control bits decode the internal register ad-
dress. On the rising edge of LE, data stored in the shift register is loaded into one of the 4 appropriate latches (selected by ad-
dress bits). Data is shifted in MSB first.
2.1.1
When LE transitions high, data is transferred from the 18-bit shift register into one of the 4 appropriate internal latches depending
upon the state of the control (CTL) bits. The control bits decode the internal register address
2.1.2 Register Content Truth Table
2.2 PROGRAMMABLE REFERENCE DIVIDERS
2.2.1 AUX_R Register
If the Control Bits (CTL [1:0]) are 0 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which
sets the Aux PLL 12-bit R counter divide ratio. The divide ratio is programmed using the bits AUX_R_CNTR as shown in table
2.2.3. The divider ratio must be
AUX_R
AUX_N
MAIN_R
MAIN_N
AUX_R
Register Location Truth Table
First Bit
First Bit
17
17
CP_WORD
FoLD[3:0]
16
16
FoLD
15
15
MSB
18
2. The FoLD word bits controls the multifunction FoLD output as described in section in 2.5.
14
14
0
0
1
1
CTL [1:0]
13
13
DATA [15:0]
AUX_B_CNTR
MAIN_B_CNTR and MAIN_A_CNTR
(Continued)
12
12
0
1
0
1
SHIFT REGISTER BIT LOCATION
SHIFT REGISTER BIT LOCATION
11
11
AUX_R Register
AUX_N Register
MAIN_R Register
MAIN_N Register
10
10
6
2 1
AUX_R_CNTR[11:0]
9
9
1.9 POWER CONTROL
Each PLL is individually power controlled by the device EN
pin. The EN
trols the Aux PLL. Activation of EN = LOW (power down)
condition results in the disabling of the respective N and R
counters and de-biasing of their respective fin inputs (to a
high impedance state). The reference oscillator input block
powers down and the OSC
state only when both EN pins are LOW. Power down forces
the respective charge pump and phase comparator logic to a
TRI-STATE condition as well as disabling the bandgap refer-
ence block. Power up occurs immediately when the EN pin is
brought high. Power up sequence: Bandgap and Oscillator
blocks come up first, with the remaining PLL functions be-
coming active approx. 1 µs later. All programming informa-
tion is retained internally in the chip when in power down
mode. The MICROWIRE control register remains active and
capable of loading and latching in data during power down
mode.
DATA Location
MAIN_R_CNTR
AUX_R_CNTR
CTL [1:0]
8
8
LSB
7
7
MAIN
0
6
6
controls the Main PLL, and the EN
5
5
AUX_A_CNTR
IN
4
4
pin reverts to a high impedance
3
3
2
2
Last Bit
Last Bit
1
0
0
1
1
1
0
AUX
0
0
1
0
1
0
0
con-