74ACT715 Fairchild Semiconductor, 74ACT715 Datasheet - Page 6

• Manufacturer Part Number: 74ACT715
• Description: Programmable Video Sync Generator
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
Addressing Logic
The register addressing logic is composed of two blocks of
logic. The first is the address register and counter
(ADDRCNTR), and the second is the address decode
(ADDRDEC).
ADDRCNTR LOGIC
Addresses for the data registers can be generated by one
of two methods. Manual addressing requires that each byte
of each register that needs to be loaded needs to be
addressed. To load both bytes of all 19 registers would
require a total of 57 load cycles (19 address and 38 data
cycles). Auto Addressing requires that only the initial regis-
ter value be specified. The Auto Load sequence would
require only 39 load cycles to completely program all regis-
ters (1 address and 38 data cycles). In the auto load
sequence the low order byte of the data register will be
Manual Addressing Mode
Auto Addressing Mode
Cycle #
1
2
3
4
5
6
Cycle #
1
2
3
4
5
6
Enable Auto Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing
Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Load Falling Edge
Load Falling Edge
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written first followed by the high order byte on the next load
cycle. At the time the High Byte is written the address
counter is incremented by 1. The counter has been imple-
mented to loop on the initial value loaded into the address
register. For example: If a value of 0 was written into the
address register then the counter would count from 0 to 18
before resetting back to 0. If a value of 15 was written into
the address register then the counter would count from 15
to 18 before looping back to 15. If a value greater than or
equal to 18 is placed into the address register the counter
will continuously loop on this value. Auto addressing is initi-
ated on the falling edge of LOAD when ADDRDATA is 0
and LHBYTE is 1. Incrementing and loading of data regis-
ters will not commence until the falling edge of LOAD after
ADDRDATA goes to 1. The next rising edge of LOAD will
load the first byte of data. Auto Incrementing is disabled on
the falling edge of LOAD after ADDRDATA and LHBYTE
goes low.
Load Start Address n
Load Lbyte (n)
Load Hbyte (n); Inc Counter
Load Lbyte (n 1)
Load Hbyte (n 1); Inc Counter
Load Address
Load Address m
Load Lbyte m
Load Hbyte m
Load Address n
Load Lbyte n
Load Hbyte n
Load Rising Edge
Load Rising Edge