74ACT715 Fairchild Semiconductor, 74ACT715 Datasheet - Page 4

• Manufacturer Part Number: 74ACT715
• Description: Programmable Video Sync Generator
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
Signal Specification
HORIZONTAL SYNC AND BLANK
SPECIFICATIONS
All horizontal signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is considered
pulse 1 not 0. All values of the horizontal timing registers
are referenced to the falling edge of the Horizontal Blank
signal (see Figure 1). Since the first CLOCK edge, CLOCK
#1, causes the first falling edge of the Horizontal Blank ref-
Horizontal Period (HPER)
Horizontal Blanking Width:
Horizontal Sync Width:
Horizontal Front Porch:
VERTICAL SYNC AND BLANK SPECIFICATION
All vertical signals are defined in terms of number of lines
per frame. This is true in both interlaced and noninterlaced
modes of operation. Care must be taken to not specify the
Vertical Registers in terms of lines per field. Since the first
CLOCK edge, CLOCK #1, causes the first falling edge of
the Vertical Blank (first Horizontal Blank) reference pulse,
edges referenced to this first edge are n
where “n” is the width of the timing in question. Registers 5,
6, and 7 are programmed in this manner. Also, in the inter-
laced mode, vertical timing is based on half-lines. There-
fore registers 5, 6, and 7 must contain a value twice the
total horizontal (odd and even) plus 1 (as described
above). In non-interlaced mode, all vertical timing is based
on whole-lines. Register 8 is always based on whole-lines
and does not add 1 for the first clock. The vertical counter
starts at the value of 1 and counts until the value of VMAX.
No restrictions exist on the values placed in the vertical
registers. Vertical Blank will change on the leading edge of
HBLANK. Vertical Sync will change on the leading edge of
HSYNC. (See Figure 2.) Vertical Frame Period (VPER)
REG(8)
Vertical Field Period (VPER/n)
Vertical Blanking Width
hper
[REG(7)
[REG(2)
[REG(1)
REG(4)
[REG(3)
REG(8)
1]
FIGURE 1. Horizontal Waveform Specification
REG(1)]
1]
ckper
hper/n
1]
ckper
hper/n
1 lines away,
ckper
ckper
4
erence pulse, edges referenced to this first Horizontal edge
are n
ing in question. Registers 1, 2, and 3 are programmed in
this manner. The horizontal counters start at 1 and count
until HMAX. The value of HMAX must be divisible by 2.
This limitation is imposed because during interlace opera-
tion this value is internally divided by 2 in order to generate
serration and equalization pulses at 2
quency. Horizontal signals will change on the falling edge
of the CLOCK signal. Signal specifications are shown
below.
Vertical Syncing Width
Vertical Front Porch
where
COMPOSITE SYNC AND BLANK SPECIFICATION
Composite Sync and Blank signals are created by logically
ANDing (ORing) the active LOW (HIGH) signals of the cor-
responding vertical and horizontal components of these
signals. The Composite Sync signal may also include ser-
ration and/or equalization pulses. The Serration pulse inter-
val occurs in place of the Vertical Sync interval.
Equalization pulses occur preceding and/or following the
Serration pulses. The width and location of these pulses
can be programmed through the registers shown below.
(See Figure 3.)
Horizontal Equalization PW
Horizontal Serration PW:
Where
1 CLOCKs away, where “n” is the width of the tim-
n
n
REG 9
REG(10)]
REG 10
n
ization
n
ization
n
1 for noninterlaced
2 for interlaced
2 for noninterlaced double serration/equal-
2 for interlaced operation
1 for noninterlaced single serration/equal-
[REG(5)
(HFP)
(HFP)
[REG(6)
ckper
[REG(4)/n
[REG(9)
(HEQP)
(HPER/2)
1]
REG(5)]
hper/n
REG(1)]
the horizontal fre-
1
(HSERR)
hper/n
REG(1)
ckper
1