74ACT715 Fairchild Semiconductor, 74ACT715 Datasheet - Page 3

• Manufacturer Part Number: 74ACT715
• Description: Programmable Video Sync Generator
• Manufacturer: Fairchild Semiconductor

(DEFAULT)
Register Description
All of the data registers are 12 bits wide. Width’s of all
pulses are defined by specifying the start count and end
count of all pulses. Horizontal pulses are specified with-
respect-to the number of clock pulses per line and vertical
pulses are specified with-respect-to the number of lines per
frame.
REG0—STATUS REGISTER
The Status Register controls the mode of operation, the
signals that are output and the polarity of these outputs.
The default value for the Status Register is 0 (000 Hex) for
the ACT715 and is “1024” (400 Hex) for the ACT715-R.
Double Equalization and Serration mode will output equal-
ization and serration pulses at twice the HSYNC frequency
(i.e., 2 equalization or serration pulses for every HSYNC
pulse). Single Equalization and Serration mode will output
an equalization or serration pulse for every HSYNC pulse.
In Interlaced mode equalization and serration pulses will be
output during the VBLANK period of every odd and even
field. Interlaced Single Equalization and Serration mode is
not possible with this part.
Bits 5–8
Bits 5 through 8 control the polarity of the outputs. A value
of zero in these bit locations indicates an output pulse
active LOW. A value of 1 indicates an active HIGH pulse.
B5—
B6—
B7—
B8—
Bits 9–11
Bits 9 through 11 enable several different features of the
device.
B9—
B
(DEFAULT)
B
0
0
0
0
1
1
1
1
0
0
1
1
2
4
B
0
0
1
1
0
0
1
1
1
B
0
1
0
1
3
B
0
1
0
1
0
1
0
1
0
Interlaced Double Serration and
Equalization
Non Interlaced Double Serration
Illegal State
Non Interlaced Single Serration and Equalization
VCBLANK Polarity
VCSYNC Polarity
HBLHDR Polarity
HSYNVDR Polarity
Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
VCBLANK VCSYNC HBLHDR HSYNVDR
CBLANK
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
Bits 0–2
Bits 3–4
Mode of Operation
CSYNC
CSYNC
VSYNC
CSYNC
CSYNC
VSYNC
VSYNC
VSYNC
HBLANK
HBLANK
HBLANK
HBLANK
CUSOR
CUSOR
HGATE
HGATE
HSYNC
HSYNC
HSYNC
HSYNC
VGATE
VGATE
VINT
VINT
3
B10—
B11—
HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizon-
tal Sync and Blank pulses.
REG1—
REG2—
REG3—
REG4—
VERTICAL INTERVAL REGISTERS
The Vertical Interval Registers determine the number of
lines per frame, and the characteristics of the Vertical Blank
and Sync Pulses.
REG5—
REG6—
REG7—
REG8—
EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS
These registers determine the width of equalization and
serration pulses and the vertical interval over which they
occur.
REG 9—
REG10—
REG11—
REG12—
VERTICAL INTERRUPT SPECIFICATION REGISTERS
These Registers determine the width of the Vertical Inter-
rupt signal if used.
REG13—
REG14—
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating sig-
nals.
REG15—
REG16—
REG17—
REG18—
Disable System Clock (0)
Enable System Clock (1)
Default values for B10 are “0” in the ACT715
and “1” in the ACT715-R.
Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for
internal testing only.
Horizontal Front Porch
Horizontal Sync Pulse End Time
Horizontal Blanking Width
Horizontal Interval Width # of Clocks
per Line
Vertical Front Porch
Vertical Sync Pulse End Time
Vertical Blanking Width
Vertical Interval Width
per Frame
Equalization Pulse Width End Time
Serration Pulse Width End Time
Equalization/Serration Pulse Vertical
Interval Start Time
Equalization/Serration Pulse Vertical
Interval End Time
Vertical Interrupt Activate Time
Vertical Interrupt Deactivate Time
Horizontal Cursor Position Start Time
Horizontal Cursor Position End Time
Vertical Cursor Position Start Time
Vertical Cursor Position End Time
# of Lines
www.fairchildsemi.com