ISL1219 Intersil Corporation, ISL1219 Datasheet - Page 17

• Manufacturer Part Number: ISL1219
• Description: Real Time Clock/Calendar
• Manufacturer: Intersil Corporation

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After these registers are set, an alarm will be generated when
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1 – Alarm set with single interrupt (IM = ”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm registers as follows:
B. Also the ALME bit must be set as follows:
xx indicate other control bits
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ output low.
Example 2 – Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm registers as follows:
REGISTER
REGISTER
REGISTER
CONTROL
ALARM
ALARM
MNA
MOA
DWA
SCA
HRA
MOA
DWA
DTA
MNA
HRA
SCA
DTA
INT
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0 HEX
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
0 0 0 0 0 0 0 0 00h Minutes disabled
0 0 0 0 0 0 0 0 00h Hours disabled
0 0 0 0 0 0 0 0 00h Date disabled
0 0 0 0 0 0 0 0 00h Month disabled
0 0 0 0 0 0 0 0 00h Day of week disabled
7 6 5 4 3 2 1 0 HEX
0 1 x
x 0 0 0 0
BIT
BIT
BIT
17
B0h Minutes set to 30,
00h Seconds disabled
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
x0h Enable Alarm
enabled
DESCRIPTION
enabled
enabled
enabled
enabled
disabled
DESCRIPTION
DESCRIPTION
ISL1219
B. Set the Interrupt register as follows:
xx indicate other control bits
Once the registers are set, the following waveform will be
seen at IRQ-:
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
User Registers
Addresses [12h to 13h]
These registers are 2 bytes of battery-backed user memory
storage.
Time Stamp Registers
Addresses [14h to 19h]
These registers contain the time stamp information in a similar
format to the RTC registers. When a valid Event is triggered at
the EVIN pin (low to high transition), these registers record the
values from the RTC registers. At the same time the EVT bit is
set and the EVDET- pin changes state (if it is enabled). The six
registers include second, minute, hour, date, month and year of
the event. Day of week is not recorded as it is not normally
required and is arbitrarily set.
Only the first Event in a series of events is time stamped, all
subsequent events are ignored. The current time stamp is
retained until the EVT bit is cleared and the next Event
occurs (EVIN pin is triggered). The contents of these
registers are cleared only after full power cycling.
I
The ISL1219 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is the master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL1219
operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
REGISTER
CONTROL
2
C Serial Interface
INT
RTC AND ALARM REGISTERS ARE BOTH “30” SEC
7 6 5 4 3 2 1 0 HEX
1 1 x x 0 0 0 0 x0h Enable Alarm and Int
BIT
60 SEC
2
C interface is conducted by
Mode
DESCRIPTION
August 14, 2006
FN6314.1