ISL1219 Intersil Corporation, ISL1219 Datasheet - Page 10

• Manufacturer Part Number: ISL1219
• Description: Real Time Clock/Calendar
• Manufacturer: Intersil Corporation

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Event Detect Timing Diagram With
Sampling Mode Enabled
Case 1, Switched Opened Before I
Case 2, Switched Opened After I
Case 3, Switched Bounced
The ISL1219 can operate independently or in conjunction
with a microcontroller for low power operation modes or in
battery backup modes.
The event detection and time stamp circuits operate in either
main V
EXT.
SWITCH
EXT.
SWITCH
EVDET
EVDET
EXT.
SWITCH
EV
EV
EV
EVDET
I
I
I
pu
pu
pu
IN
IN
IN
DD
CLOSED
CLOSED
LOW
LOW
CLOSED
LOW
power or battery backup mode.
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
OFF
OPEN
OFF
OPEN
OFF
OPEN
ON
ON
ON
10
8 CLKS (8x)
8 CLKS (8x)
15 CLKS (8x)
15 CLKS (8x)
15 CLKS (8x)
8 CLKS (8x)
pu
pu
ISL1219
Users have the option to connect EVIN (see EVINEB bit) to
an internal pull-up current source that operates at 1
(always on mode), which can drop to 400nA in battery
backup mode. User selectable event sampling modes are
also available which will effectively reduce power
consumption with 1/4-Hz, 1-Hz and 2-Hz sample detection
rates. The EVIN input is pulsed ON/OFF when in sampling
mode for power savings advantages (See tables below).
The EVIN also has a user selectable time based hysteresis
filter (see EHYS bits) to implement switch de-bouncing
during an event detection. The EVIN signal must be high for
the duration of the selected time period. The time periods
available are 0 times delay (no time based hysteresis) to
3.9ms, 15.625ms or 31.25ms (see Table 1, 2, 3, and 4).
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation
of second, minute, hour, day of week, date, month, and year.
The RTC also has leap-year correction. The clock also
corrects for months having fewer than 31 days and has a bit
that controls 24 hour or AM/PM format. When the ISL1219
powers up after the loss of both V
not begin incrementing until at least one byte is written to the
clock register.
TABLE 3. ∆I
TABLE 4. ∆I
TABLE 2. ∆I
TABLE 1. ∆I
1/4Hz
1/4Hz
1/4Hz
1/4Hz
f
f
f
f
1Hz
2Hz
1Hz
2Hz
SMP
SMP
1Hz
2Hz
1Hz
2Hz
SMP
SMP
DD
DD
DD
DD
(V
(V
(V
DD
DD
(V
DD
DD
=3.0V, t
=5.0V, t
=5.0V, t
=3V, t
DD
HYS
HYS
and V
HYS
HYS
=15.625ms)
=15.625ms)
DELTA I
DELTA I
DELTA I
DELTA I
=3.9ms)
263.3nA
526.5nA
=3.9ms)
656.3nA
20.5nA
65.8nA
1.05µA
164nA
328nA
264nA
BAT
2.1µA
82nA
82nA
, the clock will
DD
DD
DD
DD
August 14, 2006
µA
FN6314.1