ISL1219 Intersil Corporation, ISL1219 Datasheet - Page 14

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ISL1219

Manufacturer Part Number
ISL1219
Description
Real Time Clock/Calendar
Manufacturer
Intersil Corporation
Datasheet

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1Hz signal is synchronized to the STOP condition during a
valid write cycle.
CRYSTAL OSCILLATOR ENABLE BIT (XTOSCB)
This bit enables/disables the internal crystal oscillator. When
the XTOSCB is set to “1”, the oscillator is disabled, and the
X1 pin allows for an external 32kHz signal to drive the RTC.
The XTOSCB bit is set to “0” on power up.
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT and
ALM, EVT status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the Status
Register (with a valid STOP condition). When the ARST is
cleared to “0”, the user must manually reset the BAT, ALM,
and EVT bits.
INTERRUPT CONTROL REGISTER (INT)
The interrupt control register contains Frequency Output,
Alarm, and Battery switchover control bits.
NOTE: Writing to register 08h has restrictions. If V
byte writes to register 08h are allowed, only page writes beginning
with register 07h. If V
allowed, as well as page writes.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
08h
Default
ADDR
FREQUENCY,
32768
F
TABLE 7. INTERRUPT CONTROL REGISTER (INT)
4096
1024
1/16
1/32
TABLE 8. FREQUENCY SELECTION OF F
OUT
1/2
1/4
1/8
64
32
16
0
8
4
2
1
IM ALME LPMODE FOBATB FO3 FO2 FO1 FO0
7
0
6
0
UNITS
DD
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
>V
5
0
BAT
FO3
, then a byte write to register 08h IS
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
14
4
0
FO2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
3
0
BAT
FO1
OUT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
2
0
>V
DD
PIN
1
0
, then no
FO0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
ISL1219
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/F
Table 8 for frequency selection. When the frequency mode is
enabled, it will override the alarm mode at the IRQ/F
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the F
backup mode (i.e. V
FOBATB is set to “1” the F
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the F
during battery backup mode.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
V
V
power mode and the V
V
about 600nA when using LPMODE = “1” with V
(See Typical Performance Curves: I
LPMODE ON & OFF.)
It should be noted that any writes to the LPMODE bit that
may put the device into Low Power Mode should be avoided
if V
the I2C interface (until V
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/F
triggered by the alarm as defined by the alarm registers (0Ch
to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/F
tied low until the ALM status bit is cleared to “0”.
BAT
DD
DD
DD
< V
< V
supply will be used when V
IM BIT
<V
TRIP
0
1
BAT
BAT
, as the device will no longer communicate over
. With LPMODE = “1”, the device will be in low
- V
BATHYS
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By Alarm
BAT
BAT
INTERRUPT/ALARM FREQUENCY
DD
. There is a supply current saving of
power source active). When the
TABLE 9.
OUT
supply will be used when
rises above V
OUT
/IRQ pin is disabled during
OUT
OUT
DD
/IRQ pin during battery
DD
/IRQ pin is enabled
pin when the RTC is
< V
vs V
OUT
BAT
BAT
OUT
DD
- V
pin. See
).
DD
with
BATHYS
pin will be
August 14, 2006
= 5V.
OUT
FN6314.1
and
pin.

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