FIDO1100PQF208IR1 Innovasic Semiconductor Inc., FIDO1100PQF208IR1 Datasheet - Page 77

• Manufacturer Part Number: FIDO1100PQF208IR1
• Description: 32-bit Real-time Communications Controller
• Manufacturer: Innovasic Semiconductor Inc.

Flexible Input Deterministic Output (fido ® )
32-Bit Real-Time Communications Controller
Workaround:
commanded conversion (single channel or multi-channel):
Errata No. 2
Problem: Fatal fault recovery sequence can be disturbed by interrupts.
Description:
Context Fatal Faults can occur if a context's stack pointer becomes corrupted. It is a feature of
the hardware to detect this "Fatal Fault" and allow a graceful recovery by directing an exception
to the Master Context. This operation can be disturbed if, by chance, an interrupt is triggered
during a bus cycle leading to a Fatal Fault. This problem occurs no matter which context the
interrupt is directed to. It need not be the faulting context. Furthermore, since neither interrupt
timing nor fatal faults are predictable, there is no way to guarantee this cannot happen. The effect
of this error depends on the interrupt mode of the context to which the interrupt is directed. If the
interrupted context is running in Fast Single Threaded mode, when an interrupt targeted to it
occurs during a faulting bus cycle (caused by another context) the CPU will lock up after the
faulting bus cycle completes. If the interrupted context is in Standard or Fast Vectored mode the
CPU will not lock up but the normal fault handling process will be disrupted. The effect is:
An ADC interrupt will be issued if ADC interrupts are enabled. ADC interrupts are
enabled by setting ADC Control Register Bit 3 (IRQ_En) to 1.
ADC Data Available Register will correctly indicate which channels have updated results
in their Data Registers.
Clear ADC Control Register Bit 7 (EN) to 0.
Set ADC Control Register Bit 7 (EN) to 1.
Set ADC Start Register Bit 0 (START) to 1 to start the conversion process.
ADC Conversion complete will be indicated by:
– An ADC interrupt, if ADC Control Register Bit 3 (IRQ_En) is set to 1.
– ADC Control Register Bit 4 (CD-Conversion Done) will set to indicate that
Both the interrupted and the faulting context will be set to Halted.
The fatal fault exception will be directed to the interrupted context rather than the Master.
The expected interrupt will be directed (queued behind the fatal fault exception) to the
interrupted context.
conversion(s) are done.
When using non-scanning mode conversions, enable the ADC between each
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Page 77 of 81
IA211080807-06
November 20, 2009
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