FIDO1100PQF208IR1 Innovasic Semiconductor Inc., FIDO1100PQF208IR1 Datasheet - Page 67

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FIDO1100PQF208IR1

Manufacturer Part Number
FIDO1100PQF208IR1
Description
32-bit Real-time Communications Controller
Manufacturer
Innovasic Semiconductor Inc.
Datasheet

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FIDO1100PQF208IR1
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Flexible Input Deterministic Output (fido ® )
32-Bit Real-Time Communications Controller
9.2.3 SDRAM Read Operation Timing
READ bursts are initiated with a READ command.
The starting column and bank addresses are provided with the READ command, and auto
precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the burst. For the generic READ
commands used in the following illustrations, auto precharge is disabled (see Figure 27).
During READ bursts, the valid data-out element from the starting column address will be
available following the CAS latency after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go
high, and full-page burst will continue until terminated. (At end of the page, it will wrap to
column 0 and continue.)
9.2.4 SDRAM Read Burst Timing
Data from any READ burst may be truncated with subsequent READ command, and data from a
fixed-length READ burst may be immediately followed by data from a READ command. In
either case, a continuous flow of data can be maintained. The first data element from the new
burst follows either the last element of a completed burst or the last desired data element of a
®
Figure 27. SDRAM Read Operation Timing
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Page 67 of 81
IA211080807-06
November 20, 2009
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