PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 20
![no-image](/images/no-image-200.jpg)
PM4328-PI
Manufacturer Part Number
PM4328-PI
Description
Framer, T1|E1|T3 Standard Format, 324-BGA
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM4328-PI.pdf
(250 pages)
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PM4328-PI
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STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
· Detects and validates bit-oriented codes in the C-bit parity far end alarm and
· Terminates the C-bit parity path maintenance data link with an integral HDLC
· Programmable pseudo-random test-sequence detection–(up to 2 32 -1 bit
DS3 Transmit Section:
· Provides the overhead bit insertion for a DS3 stream.
· Provides a bit serial clock and data interface, and allows the M-frame
· Provides B3ZS encoding.
· Generates an B3Zs encoded 100… repeating pattern to aid in pulse mask
· Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS)
· Provides optional automatic insertion of far end receive failure (FERF) on
· Provides diagnostic features to allow the generation of line code violation
· Supports insertion of bit-oriented codes in the C-bit parity far end alarm and
· Optionally inserts the C-bit parity path maintenance data link with an integral
· Provides programmable pseudo-random test sequence generation (up to
control channel.
receiver having a 128-byte deep FIFO buffer with programmable interrupt
threshold. Supports polled or interrupt-driven operation. Selectable none,
one or two address match detection on first byte of received packet.
length patterns conforming to ITU-T O.151 standards) and analysis features.
boundary and/or the overhead bit positions to be located via an external
interface
testing.
and the idle signal when enabled by internal register bits.
detection of loss of signal (LOS), out of frame (OOF), alarm indication signal
(AIS) or red alarm condition.
error events, parity error events, framing bit error events, and when enabled
for the C-bit parity application, C-bit parity error events, and far end block
error (FEBE) events.
control channel.
HDLC transmitter. Supports polled and interrupt-driven operation.
2 32 -1 bit length sequences conforming to ITU-T O.151 standards) or any
ISSUE 1
7
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3
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