ST72324LS4 STMicroelectronics, ST72324LS4 Datasheet - Page 73

• Manufacturer Part Number: ST72324LS4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72324LS4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

10.4 SERIAL PERIPHERAL INTERFACE (SPI)
10.4.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.4.2 Main Features
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Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
Figure 43. Serial Peripheral Interface Block Diagram
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
MOSI
MISO
CPU
SCK
SS
/2 max. slave mode frequency (see note)
SOD
bit
SPIDR
8-Bit Shift Register
Read Buffer
SERIAL CLOCK
CPU
GENERATOR
CONTROL
MASTER
/4 max.)
Data/Address Bus
Read
Write
software overhead for clearing status flags and to
initiate the next transmission sequence.
10.4.3 General Description
Figure 43
(SPI) block diagram. There are 3 registers:
The SPI is connected to external devices through
3 pins:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
– SS: Slave select:
put by SPI slaves
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
7
SPIE
SPIF WCOL
7
SPE
shows the serial peripheral interface
CONTROL
SPR2
OVR
STATE
SPI
Interrupt
request
MODF
MSTR
CPOL
0
CPHA
SOD
SS
ST72324Lxx
SPICR
SPICSR
SSM
SPR1
0
1
SPR0
SSI
0
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0
1