ST72324LS4 STMicroelectronics, ST72324LS4 Datasheet - Page 119

• Manufacturer Part Number: ST72324LS4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72324LS4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

CLOCK CHARACTERISTICS (Cont’d)
12.5.5 PLL Characteristics
Note:
1. Instantaneous PLL jitter is the absolute maximum deviation on a single clock period. Data characterized, not tested in
production.
Figure 64. PLL Clock Jitter vs. Application
Signal frequency
Note 1: Measurement conditions: f
V
f
OSC
∆ f
DD(PLL)
Symbol
CPU
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
/f
CPU
2000
PLL Operating Range
PLL input frequency range
Instantaneous PLL jitter
Application Signal Frequency (KHz)
1
1000
Parameter
500
250
CPU
1)
FLASH
DEVICES
ROM
DEVICES
= 4MHz, T
125
f
OSC
= 4 MHz. (f
A
Conditions
= 25°C
PLL clock jitter may cause application errors if high
frequency signals are input or output by the appli-
cation (e.g. high speed serial I/O or sampling of
high frequency signals).
Using the PLL increases clock jitter, however this
is a periodic effect which is absorbed over several
CPU cycles. The lower the frequency of the appli-
cation signal, the less the impact.
Figure 64
out PLL) on application signals in the range
125kHz to 2MHz. At frequencies of less than
125kHz, the jitter is negligible.
CPU
=8MHz.)
shows the effect of jitter (with and with-
2.85
Min
2
Typ
3.5
ST72324Lxx
Max
3.6
5.5
4
119/154
MHz
Unit
%
V
1