ST72324LS4 STMicroelectronics, ST72324LS4 Datasheet - Page 149

• Manufacturer Part Number: ST72324LS4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72324LS4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

15 KNOWN LIMITATIONS
15.1 ALL FLASH AND ROM DEVICES
15.1.1 Safe Connection of OSC1/OSC2 Pins
The OSC1 and/or OSC2 pins must not be left un-
connected otherwise the ST7 main oscillator may
start and, in this configuration, could generate an
f
maximum (>16MHz.), putting the ST7 in an un-
safe/undefined state. Refer to
24.
15.1.2 Unexpected Reset Fetch
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
15.1.3
interrupt routine
When an active interrupt request occurs at the
same time as the related flag is being cleared, an
unwanted reset may occur.
Note: clearing the related interrupt mask will not
generate an unwanted reset
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
– The interrupt flag is cleared within any interrupt
– The interrupt flag is cleared in any part of the
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
Perform SIM and RIM operation before and after
resetting an active interrupt request.
OSC
rupt routine
routine
code while this interrupt is disabled
clock frequency in excess of the allowed
Clearing
active
interrupts
Section 6.2 on page
outside
Example:
Nested interrupt context:
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
– The interrupt flag is cleared within any interrupt
– The interrupt flag is cleared in any part of the
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
15.1.4 16-bit Timer PWM Mode
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R register
(OC1HR, OC1LR). It leads to either full or no PWM
during a period, depending on the OLVL1 and
OLVL2 settings.
15.1.5 ADC Conversion Spurious Results
Spurious conversions occur with a rate lower than
50 per million. Such conversions happen when the
measured voltage is just between 2 consecutive
digital values.
Workaround
A software filter should be implemented to remove
erratic conversion results whenever they may
cause unwanted consequences.
In order to have the accuracy specified in the da-
tasheet, the first conversion after a ADC switch-on
has to be ignored.
rupt routine
routine with higher or identical priority level
code while this interrupt is disabled
SIM
reset interrupt flag
RIM
PUSH CC
SIM
reset interrupt flag
POP CC
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