ST72324K4 STMicroelectronics, ST72324K4 Datasheet - Page 84

• Manufacturer Part Number: ST72324K4
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324K4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72324Jx ST72324Kx
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.5 Error Flags
10.4.5.1 Master Mode Fault (MODF)
Master mode fault occurs when the master device
has its SS pin pulled low.
When a Master mode fault occurs:
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
10.4.5.2 Overrun Condition (OVR)
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
Figure 51. Clearing the WCOL bit (Write Collision Flag) Software Sequence
84/164
1
1st Step
2nd Step
– The MODF bit is set and an SPI interrupt re-
– The SPE bit is reset. This blocks all output
– The MSTR bit is reset, thus forcing the device
quest is generated if the SPIE bit is set.
from the device and disables the SPI periph-
eral.
into slave mode.
MODF bit is set.
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step
Read SPICSR
Read SPIDR
RESULT
SPIF =0
WCOL=0
Read SPIDR
Read SPICSR
RESULT
WCOL=0
not cleared the SPIF bit issued from the previously
transmitted byte.
When an Overrun occurs:
– The OVR bit is set and an interrupt request is
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
The OVR bit is cleared by reading the SPICSR
register.
10.4.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode. See also
Management.
Note: a “read collision” will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see
generated if the SPIE bit is set.
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
Figure
Section 10.4.3.2 Slave Select
51).