ST72324K4 STMicroelectronics, ST72324K4 Datasheet - Page 128

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ST72324K4

Manufacturer Part Number
ST72324K4
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72324K4

Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
16-bit Timer A With
1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
16-bit Timer B With
2 input captures, 2 output compares, PWM and pulse generator modes

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Part Number:
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ST72324Jx ST72324Kx
CLOCK CHARACTERISTICS (Cont’d)
12.6.5 PLL Characteristics
Note:
1. Data characterized but not tested.
The user must take the PLL jitter into account in the application (for example in serial communication or
sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several
CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the
PLL jitter.
Figure 68
cies of less than 125KHz, the jitter is negligible.
Figure 68. Integrated PLL Jitter vs signal frequency
Note 1: Measurement conditions: f
128/164
1
f
∆ f
OSC
Symbol
CPU
+/-Jitter (%)
/ f
1.2
0.8
0.6
0.4
0.2
CPU
1
0
shows the PLL jitter integrated on application signals in the range 125kHz to 2MHz. At frequen-
4 MHz
PLL input frequency range
Instantaneous PLL jitter
2 MHz
Parameter
Application Frequency
1 MHz 500 kHz 250 kHz 125 kHz
1)
CPU
= 8MHz.
FLASH typ
ROM max
ROM typ
Flash ST72F324,
f
Flash ST72F324,
f
OSC
OSC
= 4 MHz.
= 2 MHz.
Conditions
1
Min
2
Typ
1.0
2.5
Max
2.5
4.0
4
MHz
Unit
%

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