ST72324K4 STMicroelectronics, ST72324K4 Datasheet - Page 36

• Manufacturer Part Number: ST72324K4
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324K4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72324Jx ST72324Kx
INTERRUPTS (Cont’d)
Table 8. Interrupt Mapping
Notes:
1. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■
■
■
36/164
1
N°
10
11
Falling edge
Rising edge
Falling and rising edge
0
1
2
3
4
5
6
7
8
9
21). This control allows to have up to 4 fully
MCC/RTC
TIMER A
TIMER B
Source
RESET
Block
TRAP
AVD
SCI
SPI
ei0
ei1
ei2
ei3
Reset
Software interrupt
Main clock controller time base interrupt
External interrupt port A3..0
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
SPI peripheral interrupts
TIMER A peripheral interrupts
TIMER B peripheral interrupts
SCI Peripheral interrupts
Auxiliary Voltage detector interrupt
Not used
Not used
Description
■
■
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
Register
MCCSR
SPICSR
SCISR
SICSR
Label
TASR
TBSR
N/A
N/A
Priority
Priority
Priority
Higher
Order
Lower
ACTIVE
HALT
HALT/
from
Exit
yes
yes
yes
yes
yes
yes
yes
no
no
no
no
no
1)
FFECh-FFEDh
FFFCh-FFFDh
FFEEh-FFEFh
FFEAh-FFEBh
FFFEh-FFFFh
FFFAh-FFFBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
Address
Vector