ST72324K4 STMicroelectronics, ST72324K4 Datasheet - Page 71

• Manufacturer Part Number: ST72324K4
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324K4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

16-BIT TIMER (Cont’d)
10.3.4 Low Power Modes
10.3.5 Interrupts
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
* In Flash devices, the ICF2 and OCF2 bits are forced by hardware to 0 in Timer A, hence there is no in-
terrupt event for these flags.
10.3.6 Summary of Timer modes
1) See note 4 in
2) See note 5 and 6 in
3) See note 4 in
4) In Flash devices, the TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2
5) In Flash devices, Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0.
WAIT
HALT
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
PWM Mode
Mode
event cannot be generated, OCF2 is forced by hardware to 0.
MODES
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
Section 10.3.3.5 One Pulse Mode
Section 10.3.3.6 Pulse Width Modulation Mode
Section 10.3.3.5 One Pulse Mode
Interrupt Event
Input Capture 1
Yes
Yes
No
No
Not
Recommended
Not
Recommended
Input Capture 2
Description
Yes
Yes
TIMER RESOURCES
2)5)
5)
1)5)
3)5)
Output Compare 1 Output Compare 2
OCF2
Event
OCF1
ICF2
ICF1
Flag
TOF
Yes
Yes
No
No
*
*
ST72324Jx ST72324Kx
Control
Enable
OCIE
TOIE
ICIE
Bit
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Partially
Yes
Yes
No
4)
4)
from
Halt
Exit
71/164
No
No
No
No
No
2)
1