ST72324K4 STMicroelectronics, ST72324K4 Datasheet - Page 34

• Manufacturer Part Number: ST72324K4
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324K4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72324Jx ST72324Kx
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
CPU CC REGISTER INTERRUPT BITS
Read/Write
Reset Value: 111x 1010 (xAh)
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt soft-
ware priority.
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
*Note: TRAP and RESET events can interrupt a
level 3 program.
34/164
1
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable*)
Interrupt Software Priority
7
1
1
I1
H
I0
Level
High
Low
N
I1
1
0
0
1
Z
I0
0
1
0
1
C
0
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
These four registers contain the interrupt software
priority of each interrupt vector.
– Each interrupt vector (except RESET and TRAP)
– Each I1_x and I0_x bit value in the ISPRx regis-
– Level 0 can not be written (I1_x=1, I0_x=0). In
The RESET, and TRAP vectors have no software
priorities. When one is serviced, the I1 and I0 bits
of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
ters has the same meaning as the I1 and I0 bits
in the CC register.
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
ISPR0
ISPR1
ISPR2
ISPR3
Vector address
FFFBh-FFFAh
FFE1h-FFE0h
FFF9h-FFF8h
I1_11 I0_11 I1_10 I0_10 I1_9
I1_3
I1_7
7
1
...
I0_3
I0_7
1
I1_2
I1_6
1
I0_2
I0_6
1
I1_13 and I0_13 bits
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
I1_13 I0_13 I1_12 I0_12
I1_1
I1_5
ISPRx bits
I0_1
I0_5
I0_9
...
I1_0
I1_4
I1_8
I0_0
I0_4
I0_8
0