ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 43

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ST7DALIF2

Manufacturer Part Number
ST7DALIF2
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7DALIF2

8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention
20 years at 55°C.
256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55°C.
Clock Sources
Internal 1% RC oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt
ST7DALIF2
9.7.3
Figure 18. Using the AVD to monitor V
Low power modes
Table 12.
Interrupts
The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Table 13.
AVD event
AVDF bit
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
LVD RESET
V
V
V
V
IT+(AVD)
IT+(LVD)
IT-(LVD)
IT-(AVD)
Mode
Wait
Halt
Interrupt event
V
Effect of low power modes on SI
Interrupt control bits
DD
0
No effect on SI. AVD interrupts cause the device to exit from Wait mode.
The SICSR register is frozen.
The AVD remains active.
1
INTERRUPT Cleared by
V
Early warning interrupt
(Power has dropped, MCU not
not yet in reset)
hyst
Event
reset
AVDF
flag
DD
RESET
Description
Supply, reset and clock management
control
Enable
AVDIE
bit
1
from
Wait
Exit
Yes
INTERRUPT Cleared by
hardware
0
from
Exit
Halt
No
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