ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 152

no-image

ST7DALIF2

Manufacturer Part Number
ST7DALIF2
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7DALIF2

8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention
20 years at 55°C.
256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55°C.
Clock Sources
Internal 1% RC oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt
Electrical characteristics
Note:
152/171
1
2
Table 88.
1. Data based on design simulation and/or characterisation results, not tested in production.
2. Depends on f
Figure 89. SPI slave timing diagram with CPHA=0
Measurement points are done at CMOS levels: 0.3xV
When no communication is on-going the data output line of the SPI (MOSI in master mode,
MISO in slave mode) has its alternate function capability released. In this case, the pin
status depends on the I/O port configuration.
t
Symbol
t
t
t
su(SS)
h(SS)
w(SCKH)
t
w(SCKL)
t
t
t
t
t
dis(SO)
t
t
t
su(MI)
t
v(MO)
h(MO)
su(SI)
a(SO)
v(SO)
h(SO)
h(MI)
h(SI)
MISO
MOSI
SS
(1)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
(1)
OUTPUT
INPUT
INPUT
SS setup time
SS hold time
SCK high and low
time
Data input setup time
Data input hold time
Data output access
time
Data output disable
time
Data output valid
time
Data output hold time
Data output valid
time
Data output hold time
SPI characteristics (continued)
see note 2
CPU
Parameter
. For example, if f
t
a(SO)
t
su(SS)
t
su(SI)
(2)
t
t
MSB IN
w(SCKH)
w(SCKL)
MSB OUT
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable
edge)
Master (after enable
edge)
CPU
t
t
h(SI)
c(SCK)
= 8 MHz, then T
Conditions
t
v(SO)
BIT6 OUT
CPU
BIT1 IN
= 1/ f
t
(4 x T
h(SO)
DD
CPU
and 0.7xV
CPU
Min
100
100
100
100
100
120
= 125 ns and t
90
t
t
0
0
0
r(SCK)
f(SCK)
) +150
LSB IN
LSB OUT
DD
t
h(SS)
.
SU(SS)
Max
120
240
120
120
= 550 ns
t
dis(SO)
ST7DALIF2
note 2
see
Unit
ns

Related parts for ST7DALIF2