AD6654 Analog Devices, AD6654 Datasheet - Page 9

• Manufacturer Part Number: AD6654
• Description: 14-Bit, 92.16 MSPS, 4 & 6-Channel Wideband IF to Base Band Receiver
• Manufacturer: Analog Devices

Specifications of AD6654

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 92.16MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Adc Architecture: Subranging
• Pkg Type: BGA,CSP

TIMING CHARACTERISTICS
Table 7.
Parameter
CLK TIMING REQUIREMENTS
INPUT WIDEBAND DATA TIMING REQUIREMENTS
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER)
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE)
MISC PINS TIMING REQUIREMENTS
1
2
3
All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V, and the VDDIO range of 3.0 V to 3.6 V.
C
These timing parameters are derived from the ADC ENC rate with DDC CLK driven directly from ADC DR output.
LOAD
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK
CLKL
CLKH
DEXP
DPREQ
DPP
DPIQ
DPCH
DPGAIN
SPA
HPA
PCLK
PCLKL
PCLKH
DPREQ
DPP
DPIQ
DPCH
DPGAIN
SPA
HPA
RESET
DIRP
SSYNC
HSYNC
= 40 pF on all outputs, unless otherwise noted.
1, 2, 3
CLK Period
CLK Width Low
CLK Width High
↑CLK to EXP[2:0] Delay
↑PCLK to ↑Px REQ Delay (x = A, B, C)
↑PCLK to Px[15:0] Delay (x = A, B, C)
↑PCLK to Px IQ Delay (x = A, B, C)
↑PCLK to Px CH[2:0] Delay (x = A, B, C)
↑PCLK to Px Gain Delay (x = A, B, C)
Px ACK to ↑PCLK Setup Time (x = A, B, C)
Px ACK to ↑PCLK Hold Time (x = A, B, C)
PCLK Period
PCLK Low Period
PCLK High Period
↑PCLK to ↑Px REQ Delay (x = A, B, C)
↑PCLK to Px[15:0] Delay (x = A, B, C)
↑PCLK to Px IQ Delay (x = A, B, C)
↑PCLK to Px CH[2:0] Delay (x = A, B, C)
↑PCLK to Px Gain Delay (x = A, B, C)
Px ACK to ↓PCLK Setup Time (x = A, B, C)
Px ACK to ↓PCLK Hold Time (x = A, B, C)
RESET Width Low
CPUCLK/SCLK to IRP Delay
SYNC(0, 1, 2, 3) to ↑CLK Setup Time
SYNC(0, 1, 2, 3) to ↑CLK Hold Time
Rev. 0 | Page 9 of 88
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
Min
5.154
5.154
5.98
1.77
2.07
0.48
0.38
0.23
4.59
0.90
5.0
1.7
0.7
4.72
4.8
4.83
4.88
5.08
6.09
1.0
30
7.5
0.87
0.67
Typ
10.85
0.5 × t
0.5 × t
0.5 × t
0.5 × t
CLK
CLK
PCLK
PCLK
Max
10.74
3.86
5.29
5.49
5.35
4.95
8.87
8.48
10.94
10.09
11.49
AD6654
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns