AD6654 Analog Devices, AD6654 Datasheet - Page 27

• Manufacturer Part Number: AD6654
• Description: 14-Bit, 92.16 MSPS, 4 & 6-Channel Wideband IF to Base Band Receiver
• Manufacturer: Analog Devices

Specifications of AD6654

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 92.16MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Adc Architecture: Subranging
• Pkg Type: BGA,CSP

THEORY OF OPERATION
ADC ARCHITECTURE
The AD6654 analog-to-digital converter (ADC) front end
employs a 3-stage subrange architecture. This design approach
achieves the required accuracy and speed, while maintaining
low power consumption.
The AD6654 front end has complementary analog input pins,
AIN+ and AIN−, as shown in Figure 1. Each analog input is
centered at 2.4 V and should swing ±0.55 V around this
reference (see Figure 36). Because AIN+ and AIN− are 180°
out of phase, the differential full-scale analog input signal is
2.2 V p-p.
Both analog inputs are buffered prior to the first track-and-
hold, TH1. The high state of the ENCODE pulse places TH1 in
hold mode. The held value of TH1 is applied to the input of a
5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit
digital-to-analog converter, DAC1. DAC1 requires 14 bits of
precision that is achieved through laser trimming.
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The output of DAC1 is subtracted from the delayed analog
signal at the input of TH3 to generate a first residue signal. TH2
provides an analog pipeline delay to compensate for the digital
delay of ADC1.
The first residue signal is applied to a second conversion stage
consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The
second DAC requires 10 bits of precision, which is met by the
process with no trim. The input to TH5 is a second residue
signal generated by subtracting the quantized output of DAC2
from the first residue signal held by TH4. TH5 drives a final
6-bit ADC3.
The digital outputs from ADC1, ADC2, and ADC3 are added
together and corrected in the digital error correction logic to
generate the final output data. The latency of the ADC core is
four CLK cycles. The resulting 14-bit ADC data is internally
routed directly to the integrated DDC for processing by the
4/6 independent DDC channels.
AD6654