AD6654 Analog Devices, AD6654 Datasheet
AD6654
Specifications of AD6654
Available stocks
Related parts for AD6654
AD6654 Summary of contents
Page 1
... HB2 M = 1– BYP BYP, 2 AVDD, DRVDD, SYNC CLOCK MULTIPLIER Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD6654 MRCF CRCF LHB DRCF M = 1– 1–16 MRCF CRCF LHB DRCF M = 1– 1– ...
Page 2
... AD6654 TABLE OF CONTENTS General Description ......................................................................... 4 Product Highlights ....................................................................... 5 Specifications..................................................................................... 6 Recommended Operating Conditions ...................................... 6 ADC DC Specifications ............................................................... 6 ADC Digital Specifications ......................................................... 6 ADC Switching Specifications.................................................... 7 ADC AC Specifications ............................................................... 7 Electrical Characteristics............................................................. 8 Timing Characteristics ................................................................ 9 Microport Timing Characteristics ........................................... 10 Serial Port Timing Characteristics ........................................... 11 Timing Diagrams............................................................................ 12 Absolute Maximum Ratings.......................................................... 18 Thermal Characteristics ............................................................ 18 Explanation of Test Levels ......................................................... 18 ESD Caution ...
Page 3
... Serial Port Control ..........................................................................60 Hardware Interface .....................................................................60 SPI Mode Timing........................................................................62 SPORT Mode Timing.................................................................64 Programming Indirect Addressed Registers Using Serial Port..........................................................................67 Connecting the AD6654 Serial Port to a Blackfin DSP .........69 Microport .........................................................................................70 Intel (Inm) Mode ........................................................................70 Motorola (MNM) Mode ............................................................70 Accessing Multiple AD6654 Devices .......................................71 Memory Map ...................................................................................72 Reading the Memory Map Table...............................................72 Bit Format ...
Page 4
... The DDC input port of the AD6654 has its own clock input used for latching the input data, as well as for providing the input for an onboard PLL clock multiplier. The output of the PLL clock is used for processing all filters and processing blocks beyond the data router following CIC filter ...
Page 5
... RAKE receivers. It has programmable clipping and rounding control to provide different output resolutions. The overall filter response for the AD6654 is the composite of all the combined filter stages. Each successive filter stage is capable of narrower transition bandwidths, but requires a greater number of CLK cycles to calculate the output. The AD6654 features a fractional clock multiplier that uses the ADC clock (which is slower than the DDC’ ...
Page 6
... AD6654 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Table 1. Parameter (Conditions) 1 AVDD 2 DRVDD VDDCORE 2 VDDIO T AMBIENT 1 Specified for dc supplies with linear rise-time <250 ms. 2 DRVDD and VDDIO can be operated from the same supply. ADC DC SPECIFICATIONS AVDD = 5.0 V, DRVDD = 3.3 V, VDDCORE = 1.8 V, VDDIO = 3.3 V, maximum rated sample rate, differential ENC and AIN, unless otherwise noted ...
Page 7
... ENCH Temp 25°C Full 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full Full Full Full 3 25°C 25°C Rev Page AD6654 Min Typ Max Unit 92.16 MSPS 30 MSPS 5.154 5.425 ns 5.154 5.425 ns Test Level Min Typ Max V 74 ...
Page 8
... AD6654 ELECTRICAL CHARACTERISTICS AVDD = 5.0 V, DRVDD = 3.3 V, VDDCORE = 1.8 V, VDDIO = 3.3 V, maximum rated sample rate, differential input, unless otherwise noted. Table 6. Parameter (Conditions) LOGIC INPUTS (NOT 5 V TOLERANT) Logic Compatibility Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Logic 1 Current (Inputs With Pull-Down) Logic 0 Current (Inputs With Pull-Up) ...
Page 9
... Full IV 5.0 Full IV 1.7 Full IV 0.7 Full IV 4.72 Full IV 4.8 Full IV 4.83 Full IV 4.88 Full IV 5.08 Full IV 6.09 Full IV 1.0 Full IV 30 Full V 7.5 Full IV 0.87 Full IV 0.67 Rev Page AD6654 Typ Max Unit 10.85 ns 0.5 × CLK 0.5 × CLK 10.74 ns 3.86 ns 5.29 ns 5.49 ns 5. 0.5 × PCLK 0.5 × PCLK 8.87 ns 8.48 ns 10.94 ns 10.09 ns 11. ...
Page 10
... AD6654 MICROPORT TIMING CHARACTERISTICS Table Parameter MICROPORT CLOCK TIMING REQUIREMENTS t CPUCLK Period CPUCLK t CPUCLK Low Time CPUCLKL t CPUCLK High Time CPUCLKH INM MODE WRITE TIMING (MODE = 0) to ↑CPUCLK Setup Time t 3 Control SC to ↑CPUCLK Hold Time t Control 3 HC Address/Data to ↑CPUCLK Setup Time ...
Page 11
... Temp Test Level Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Rev Page AD6654 Min Typ Max Unit 10.0 ns 1.60 0.5 × SCLK 1.60 0.5 × SCLK 1.30 ns 0.40 ns 4.12 ns −2.78 ns 4.28 7.96 ns 0.80 ns 0.40 ns 1.60 ns −0.13 ns 1.60 ns −0. ...
Page 12
... AD6654 TIMING DIAGRAMS RESET CLK CPUCLK SCLK CLK SYNC [3:0] CLK EXPx [2:0] t RESL Figure 2. Reset Timing Requirements t CLKH t CLKL Figure 3. CLK Switching Characteristics t CPUCLKH t CPUCLKL Figure 4. CPUCLK Switching Characteristics t SCLKH t SCLKL Figure 5. SCLK Switching Characteristics t t SSYNC HSYNC Figure 6. SYNC Timing Inputs ...
Page 13
... TIED LOGIC HIGH ALL THE TIME t t DPP DPP RSSI [11:0] I [15:0] Q [15:0] t DPCH PxCH [2:0] = CHANNEL NO. t DPGAIN Rev Page HPA t t DPP DPP t DPP I [15:0] Q [15:0] RSSI [11:0] t DPIQ t DPCH PxCH [2:0] = CHANNEL NO. t DPGAIN DPP DPP DPP I [15:0] Q [15:0] RSSI [11:0] t DPIQ t DPCH PxCH [2:0] = CHANNEL NO. t DPGAIN AD6654 ...
Page 14
... AD6654 CPUCLK SAM A [7:0] t SAM D [15:0] RDY NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM CPUCLK CYCLES. ACC CPUCLK SAM A [7:0] D [15:0] RDY NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM CPUCLK CYCLES. ...
Page 15
... DTACK NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM CPUCLK CYCLES. ACC Figure 13. MNM Microport Read Timing Requirements Rev Page HAM t HAM t DDTACK VALID DATA t DDTACK t ACC AD6654 HAM ...
Page 16
... AD6654 SCLK t SSCS SCS SMODE t SSDI SDI t SSRFS SRFS MODE SCLK t SSCS SCS SMODE SDO t SSTFS STFS MODE SCLK t SSCS SCS SMODE t SSDI SDI D0 MODE LOGIC 1 t HSDI HSRFS LOGIC 1 Figure 14. SPORT Mode Write Timing Characteristics LOGIC 1 t DSDO ...
Page 17
... SCLK t SSCS SCS SMODE t DSDO SDO D0 D1 MODE Figure 17. SPI Mode Read Timing Characteristics LOGIC LOGIC 0 Rev Page AD6654 t HSCS D7 ...
Page 18
... AD6654 ABSOLUTE MAXIMUM RATINGS Table 10. Parameter Rating AVDD 0 to +7.0 V DRVDD 0 to +4.0 V VDDCORE −0 +2.2 V VDDIO 0 to +4.0 V Analog/Encode Input Voltage 0 to AVDD Analog Input Current 25 mA Digital Input Voltage −0 3.6 V (not 5 V tolerant) Digital Output Voltage −0 VDDIO + 0.3 V Operating Temperature Range − ...
Page 19
... DRVDD AVDD AVDD AGND AIN+ CORE DGND DRVDD AVDD AVDD AGND AGND SYNC2 DRVDD AVDD AVDD AGND AGND – SYNC1 DRVDD AGND AGND AGND ENC SYNC3 DR AGND V REF AGND ENC AD6654 ...
Page 20
... AD6654 Name Type Pin Number DDC INPUTS CLK Input A11 SYNC0 Input T10 SYNC1 Input R11 SYNC2 Input P11 SYNC3 Input T11 DDC OUTPUTS EXPC [2:0] Output D11, C11, B11 DDC OUTPUT PORTS PCLK Bi-dir T4 PADATA[15:0] Output Table 12 See PACH[2:0] Output D8, R5, C8 ...
Page 21
... N5, D6, R4, C6,T3, B6, R3, D7, N4, C7, P4, T2, A7, N3, P3, B7 PBDATA[15:0] D9, N7, B9, C9, B10, T5, A10, P6, P7, C10, P5, R7, T6, R6, R9, D10 PCDATA[15:0] C5, N1, D5, A5, N2, B5, D4, M4, K5, M3, L5, L3, L2, M2, M1, L4 D[15:0] J3, F5, G4, H1, H3, G5, J2, B1, G2, G3, H4, H2, A3, F2, A2, F3 A[7:0] K3, J5, K4, L1, K2, K1, H5, J4 Rev Page AD6654 ...
Page 22
... AD6654 TYPICAL PERFORMANCE CHARACTERISTICS +85° ENCODE = 92.16MSPS AIN = –1dBFS 110 AIN FREQUENCY (MHz) Figure 19. ADC Noise vs. Analog Frequency (46.08 MHz BW) 120 110 dBFS 100 90 ENCODE = 92.16MSPS 80 AIN = 37.7MHz TEMPERATURE = 25°C 70 dBc SFDR = 90dB REFERENCE LINE ...
Page 23
... Figure 29. WCDMA Carrier AIN = 70 MHz; Encode = 92.16 MSPS 0 32k FFT –15 –30 –45 –60 –75 –90 –105 –120 –135 –150 Figure 30. WCDMA Carrier AIN = 151.5 MHz; Encode = 92.16 MSPS Rev Page AD6654 FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) ...
Page 24
... AD6654 0 AIN = –7dBFS –15 32k FFT F1 –30 –45 –60 –75 –90 –105 –120 –135 –150 FREQUENCY (Hz) Figure 31. CDMA Two Tones at 55 MHz and 56 MHz; ENC = 92.16 MSPS 110 100 –77 Rev Page dBFS dBc SFDR = 90dB REFERENCE LINE – ...
Page 25
... ENC– 10kΩ Rev Page AVDD REF AVDD AVDD CURRENT MIRROR C1, C2 Figure 35. ADC Compensation Pins, C1 and C2 V AVDD CH AIN+ BUF 500Ω BUF V AVDD CH 500Ω BUF AIN– Figure 36. ADC Analog Input Stage AD6654 T/H V REF T/H ...
Page 26
... Power-Supply Rise Time The time from when the dc supply is initiated until the supply output reaches the minimum specified operating voltage for the AD6654, measured at the supply pin(s) of the AD6654. Processing Gain When the tuned channel occupies less bandwidth than the input signal, this rejection of out-of-band noise is referred to as processing gain ...
Page 27
... This design approach achieves the required accuracy and speed, while maintaining low power consumption. The AD6654 front end has complementary analog input pins, AIN+ and AIN−, as shown in Figure 1. Each analog input is centered at 2.4 V and should swing ±0.55 V around this reference (see Figure 36). Because AIN+ and AIN− ...
Page 28
... To take full advantage of this high input impedance, a 20:1 transformer is required. This is a large ratio that could result in unsatisfactory performance. In this case, a lower step-up ratio could be used. The recommended method for driving the analog input of the AD6654 is to use a 4:1 impedance ratio RF transformer. For example ENC+ with a 4:1 impedance ratio transformer, the input matches Ω ...
Page 29
... MHz. The internal blocks of the AD6654 that run off the PLL clock are rated to run at a maximum of 200 MHz. The default power-up state for the PLL clock multiplier is the bypass state, where CLK is passed on as the PLL clock ...
Page 30
... External gain-ranging blocks have a delay associated with changing the gain of the signal. Typically, these delays can clock cycles. The gain change in the AD6654 (via EXP[2:0]) must be synchronized with the gain change in the gain-ranging block (external). This is allowed in the AD6654 by providing a flexible delay, programmable 6-bit word in the gain control register ...
Page 31
... ADC INPUT PORT MONITOR FUNCTION The AD6654 provides a power monitor function that can monitor the DDC input stream and gather statistics about the received signal in a signal chain. This function block can operate in one of three modes measuring the following over a programmable period of time: • ...
Page 32
... MSR value is not transferred to the holding register normal operation. The timer still generates an interrupt on the AD6654 interrupt pin and updates the interrupt status register. An interrupt appears on the IRP pin, if interrupts are enabled in the interrupt enable register. ...
Page 33
... INPUT CROSSBAR MATRIX The AD6654 has one ADC input port and six channels. Each channel can individually select its input source from either the real ADC input port, or from an internally generated pseudo random sequence (referred sequence) generator. Each channel has an input crossbar matrix to facilitate selection of the input signal source ...
Page 34
... The worst-case spurious signal from the NCO is better than −100 dBc for all output frequencies. Because all the filtering in the AD6654 is low-pass filtering, the carrier of interest is tuned down to dc (frequency = 0 Hz). This is illustrated in Figure 47. Once the signal of interest is tuned down to dc, the unwanted adjacent carriers can be rejected using the low-pass filtering that follows ...
Page 35
... The last phase in the NCO phase register is the initiating point for the new frequency. PHASE DITHER The AD6654 provides a phase dither option for improving the spurious performance of the NCO. Writing Logic 1 in the phase dither enable bit of the NCO control register of individual channels enables phase dither ...
Page 36
... AD6654 FIFTH-ORDER CIC FILTER The signal processing stage immediately after the NCO is a CIC filter stage. This stage implements a fixed coefficient, decimat- ing, cascade integrated comb filter. The input rate to this filter is the same as the data rate at the input port; the output rate from this stage is dependent on the decimation factor ...
Page 37
... Therefore, for this example, the maximum bound on CIC decimation rate higher than the 100 dB required. Rev Page the frequency that has −100 dB of alias rejection is means less alias rejection CIC AD6654 ). For an CIC ...
Page 38
... AD6654 FIR HALF-BAND BLOCK The output of the CIC filter is pipelined into the FIR HB (half- band) block. Each channel has two sets of cascading fixed coefficient FIR and fixed coefficient half-band filters. The half- band filters decimate by 2. Each of these filters (FIR1, HB1, FIR2, and HB2) is described in the following sections ...
Page 39
... HB1 is not bypassed 2 0 0.39 0.61 FIR2 RESPONSE 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 FRACTION OF FIR2 INPUT SAMPLE RATE Figure 51. FIR2 Filter Response to the Input Rate of the Filter Normalized Decimal Coefficient Coefficient (12-Bit) 0.00097656 2 −0.00537109 −11 0.015 32 −0.0380859 −78 0.0825195 169 −0.1821289 −373 0.6259766 1282 1 2048 AD6654 –30 0.9 ...
Page 40
... AD6654 control register bypasses this fixed coefficient HB filter. The filter is useful only in certain filter configurations and bypassing it for other applications results in power savings. For example, the filter is useful in narrow-band applications in which more filtering is required, as compared to wide-band applications, in which a higher output rate might prohibit the use of a decimat- ing filter ...
Page 41
... Allowing different channel back ends to select different channel front ends is useful in the polyphase implementation of filters. When multiple AD6654 channels are used to process a single carrier, a single-channel front end feeds more than one channel back end. After processing through the channel back ends (RCF filters), the data is interleaved back from all the polyphased channels ...
Page 42
... AD6654 MONO-RATE RAM COEFFICIENT FILTER (MRCF) The MRCF is a programmable sum-of-products FIR filter. This filter block comes after the first data router and before the DRCF and CRCF programmable filters. It consists of a maxi- mum of eight taps with 6-bit programmable coefficients. Note that this block does not decimate and is used as a helper filter for the DRCF and CRCF filters that follow in the signal chain ...
Page 43
... DECIMATION PHASE When more than one channel of AD6654 is used to process one carrier, polyphase implementation of corresponding channels’ DRCF or CRCF is possible using the decimation phase feature. ...
Page 44
... AD6654 PROGRAMMING DRCF REGISTERS FOR AN ASYMMETRICAL FILTER To program the DRCF registers for an asymmetrical filter: 1. Write NTAPS – the DRCF taps register, where NTAPS is the number of filter taps. The absolute maximum value for NTAPS asymmetrical filter mode. 2. Write 0 for the DRCF coefficient offset register. ...
Page 45
... DECIMATION PHASE When more than one channel of the AD6654 is used to process one carrier, polyphase implementation of the corresponding channels’ DRCF or CRCF is possible using the decimation phase feature. This feature can be used only under certain conditions ...
Page 46
... AD6654 PROGRAMMING CRCF REGISTERS FOR AN ASYMMETRICAL FILTER To program the CRCF registers for an asymmetrical filter: 1. Write NTAPS – the CRCF taps register, where NTAPS is the number of filter taps. The absolute maximum value for NTAPS asymmetrical filter mode. 2. Write 0 for the CRCF coefficient offset register. ...
Page 47
... INTERPOLATING HALF-BAND FILTER The AD6654 has interpolating half-band FIR filters that immediately follow the CRCF programmable FIR filters and precede the second data router. Each interpolating half-band filter takes 22-bit I and 22-bit Q data from the preceding CRCF and outputs rounded 22-bit I and 22-bit Q data to the second data router ...
Page 48
... AD6654 OUTPUT DATA ROUTER The output data router circuit precedes the six AGCs of the final output block and immediately follows interpolating half- band filters. This block consists of two subblocks. The first block is responsible for combining (interleaving) data from more than one channel into a single stream of data. The second block performs complex filter completion, as explained later in this section ...
Page 49
... The six AGCs available on the AD6654 are programmable through the six channel memory maps. AGCs corresponding to individual channels can be bypassed by writing Logic 1 to the AGC bypass bit in the AGC control register ...
Page 50
... AD6654 DESIRED SIGNAL LEVEL MODE In this mode of operation, the AGC strives to maintain the output signal at a programmable set level. The desired signal level mode is selected by writing Logic 0 into the AGC clipping error enable bit of the AGC control register. The loop finds the square (or power) of the incoming complex data signal by squaring I and Q and adding them ...
Page 51
... P exp 1,2 τ × Sample Rate ⎢ ⎥ ⎣ ⎦ are the time constants corresponding to Pole settling time 5 % settling time τ (CIC decimation is from 1 to 4,096), and either the settling AD6654 , are the roots 2 − and 1 ...
Page 52
... AD6654 4 exponent plus 8 mantissa bit floating-point representation similar to the error threshold. This is taken as the initial gain value before the AGC loop starts operating. The products of the gain multiplier are the AGC scaled outputs with a 19-bit representation. These are, in turn, used as I and Q for calculating the power, and the AGC error and loop are filtered to produce the signal gain for the next set of samples ...
Page 53
... PARALLEL PORT OUTPUT The AD6654 incorporates three independent 16-bit parallel ports for output data transfer. The three parallel output ports share a common clock, PCLK. Each port consists of a 16-bit data bus, request signal, acknowledge signal, three channel indicator pins, one I/Q indicator pin, one gain word indicator pin, and a common shared PCLK pin ...
Page 54
... AD6654 PCLK PxACK PxREQ Px [15:0] PxIQ PxCH [2:0] PxGAIN PCLK PxACK PxREQ Px [15:0] PxIQ PxCH [2:0] PxGAIN When an output data sample is available for output from an AGC, the parallel port initiates the transfer by pulling the PxREQ signal high. In response, the processor receiving the data needs to pull the PxACK signal high, acknowledging that it is ready to receive the signal ...
Page 55
... Slave mode PCLK signals can be either synchronous or asynchronous. The maximum slave mode PCLK frequency is also 200 MHz. t DPREQ t DPP I [15:8] Q [15:8] GAIN [11:0] t DPIQ t DPCH PxCH [2:0] = CHANNEL # Figure 60. Parallel I/Q Mode with an AGC Gain Word Rev Page PLL _ CLK rate = PCLK divisor 0000 + t DPGAIN AD6654 ...
Page 56
... Parallel Port Control 2 register output (master mode), the maximum frequency is CLK/N, where CLK is the AD6654 clock and integer divisor input (slave mode), it can be asynchronous or synchronous relative to the AD6654 CLK. This pin powers input to avoid possible contentions ...
Page 57
... USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST) Each channel of AD6654 includes a BIST block. The BIST, along with an internal test signal (pseudo random test input signal), can be used to generate a signature. This signature can be compared with a known good device and an untested device to see if the untested device is functional. ...
Page 58
... The AD6654 offers two types of synchronization: start sync and hop sync. Start sync is used to bring individual channels out of sleep after programming. It can also be used while AD6654 is operational to resynchronize the internal clocks. Hop sync is used to change or update the NCO frequency tuning word and the NCO phase offset word ...
Page 59
... Write the hop synchronization enable bit and SYNC pin enable bits high in the pin synchronization configuration register. This enables the countdown of the frequency hold-off counter. When the count reaches 1, the new frequency and/or phase offset is loaded into the NCO. Rev Page AD6654 16 ). ...
Page 60
... The pins described in Table 26 comprise the physical interface between the user’s programming device and the serial port of the AD6654. All serial pins are inputs except for SDO, which is an open-drain output and should be pulled high by an external pull-up resistor (suggested value 1 kΩ). ...
Page 61
... RD + COUNT (3) 0x83 DATA FROM BLOCK END DATA FROM BLOCK END ADDRESS ADDRESS – – 1 Rev Page AD6654 DATA TO BLOCK END ADDRESS – – 2 DATA TO BLOCK START ADDRESS + DATA FROM BLOCK END ADDRESS – – 2 ...
Page 62
... AD6654 MSBFIRST SCS BLOCK START ADDRESS SDI SDO MODE Figure 64. Serial Read of Three Bytes with MSBFIRST = 0 (All Words are Written or Read LSB First) SPI MODE TIMING In SPI mode, the SCLK should run only when data is being transferred and SCS is logic low. If SCLK runs when SCS is logic high, the internal shift register continues to run and instruction words or data are lost ...
Page 63
... Register readback data shifts out on the rising edge of SCLK. The SDO pin high impedance state at all times except during a read cycle. READ BLOCK COUNT (Nx Figure 67. SPI Read MSBFIRST = 1 Rev Page WRITE AD6654 D7 D0 ...
Page 64
... AD6654 MSBFIRST SCLK SCS SMODE BLOCK START ADDRESS SDI SDO MODE SPORT MODE TIMING In SPORT mode, the SCLK continuously runs, and the external SRFS and STFS signals are used to frame the data. Incoming framing signals SRFS (receive) and STFS (transmit) are sampled on the falling edges of SCLK ...
Page 65
... SCLK. The SDO pin high impedance state at all times except during a read operation. READ BLOCK COUNT (Nx Figure 71. SPORT Read MSBFIRST = 1 Rev Page WRITE AD6654 D7 D0 ...
Page 66
... AD6654 MSBFIRST SCLK SCS SMODE SRFS BLOCK START ADDRESS SDI STFS SDO MODE BLOCK COUNT (Nx Figure 72. SPORT Read MSBFIRST = 0 Rev Page READ ...
Page 67
... N; i++) { SerialWrite(0x9E); SerialWrite(0x81); //data bits[23:16] Coeff[i] = SerialRead() << 16; SerialWrite(0x9D); SerialWrite(0x81); //data bits[15:8] Coeff[i] |= SerialRead() << 8; SerialWrite(0x9C); SerialWrite(0x81); //data bits[7:0] Coeff[i] |= SerialRead(); } Rev Page AD6654 //writing registers //MSB written first //LSB written last //reading registers //MSB readback first //LSB readback last ...
Page 68
... AD6654 LSBFIRST Mode Using Single Byte Block Transfers SerialWrite(0x98); //CRCF Start Address SerialWrite(0x01); SerialWrite(0x00); SerialWrite(0x99); //CRCF Final Address SerialWrite(0x01); SerialWrite(N-1); //N is the number of coefficients for (i < N; i++) { // writing registers SerialWrite(0x9C); //LSB written first SerialWrite(0x01); //data bits[7:0] SerialWrite(coeff[i] & 0xFF); SerialWrite(0x9D); SerialWrite(0x01); ...
Page 69
... CONNECTING THE AD6654 SERIAL PORT TO A BLACKFIN DSP In SPI mode, the Blackfin DSP must act as a master to the AD6654 by providing the SCLK. SDO is an open-drain output, so that multiple slave devices can be connected together. Figure 73 shows a typical connection. SCLK SCK SPISS SRFS ...
Page 70
... The chip select ( active-low input that signals when an access is active on its programming port pins. During an access, the AD6654 drives RDY low to indicate that it is performing the access. When the internal read or write access is complete, the RDY pin is pulled high. Because the RDY pin is an open-drain output with a weak internal pull-up resistor (70 kΩ ...
Page 71
... ACCESSING MULTIPLE AD6654 DEVICES If multiple AD6654 devices are on a single board, the microport pins for these devices can be shared. In this configuration, a single programming device (DSP, FPGA, or microcontroller) can program all AD6654 devices connected to it. Each AD6654 has four CHIPID pins that can be connected in 16 different ways ...
Page 72
... AD6654 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has four address locations. The memory map is roughly divided into four regions: global register map (Address 0x00 to Address 0x0B), input port register map (Address 0x0C to Address 0x67), channel register map (Address 0x68 to Address 0xBB), and output port register map (Address 0xBC to Address 0xE7) ...
Page 73
... AGC3, Q Output <15:0> (read only) AGC4, Q Output <15:0> (read only) AGC5, Q Output <15:0> (read only) Open <15:12>, AGC1 RSSI Output <11:0> (read only) Open <15:12>, AGC3 RSSI Output <11:0> (read only) Open <15:12>, AGC5 RSSI Output <11:0> (read only) Rev Page AD6654 8-Bit Hex Byte 0 Address Open <7:0> 0x00 Pin Synchronization 0x04 Configuration < ...
Page 74
... Chip ID Bits. The chip ID bits are used to compare against the chip ID input pins (CHIPID), enabling or disabling I/O access for this specific chip. When more than one AD6654 part is sharing the microport, different CHIPID pins can be used to differentiate among the parts. A particular part gives I/O access only when the CHIPID pins have the same value as these chip ID bits ...
Page 75
... ADC port power monitor period). If the ADC port power monitor interrupt enable bit is cleared, the AD6654 does not set this bit and does not generate an interrupt. <1>: Reserved. This bit must be written with Logic 0. <0>: Reserved. This bit must be written with Logic 0. ...
Page 76
... AD6654 Interrupt Enable Register <15:0> <15>: AGC5 RSSI Update Enable Bit. When this bit is set, the AGC5 RSSI update interrupt is enabled, allowing an interrupt to be generated when the RSSI word is updated. When this bit is cleared, an interrupt cannot be generated for this event. Also, see the Interrupt Status Register <15:0> section. ...
Page 77
... If this bit is set, the monitoring function is cleared after the read. If this bit is Logic 0, the monitoring function is not cleared. This bit is a don’t care bit, if the disable integration counter bit is cleared. Rev Page AD6654 ...
Page 78
... AD6654 <2:1>: Monitor Function Select Bits. Table 32 describes the function of these bits. Table 32. Monitor Function Select Bits Monitor Function Select Function Enabled 00 Peak detect mode 01 Mean power monitor mode 10 Threshold crossing mode 11 Invalid selection <0>: Monitor Enable Bit. When this bit is set, the power monitoring function is enabled and operates as selected by Bit 2 to Bit 1 of the signal monitor register ...
Page 79
... DRCF Multiply Accumulate Scale Bits. The output of the DRCF filter is scaled according to the value of these bits. Table 37 lists the attenuation corresponding to each setting. Rev Page AD6654 Scale Factor 18.06 dB attenuation (left-shift 3 bits) 12.04 dB attenuation (left-shift 2 bits) 6.02 dB attenuation (left-shift 1 bit) ...
Page 80
... CRCF filter. The valid range MCRCF − 1, where MCRCF is the decimation rate of the CRCF filter. This word is primarily used for synchronization of multiple channels of the AD6654, when more than one channel is used for filtering one signal (one carrier). CRCF Coefficient Offset <5:0> ...
Page 81
... AGC Error Threshold <11:0> This 12-bit register is the comparison value used to determine which loop gain value (K 1 When the magnitude-of-error signal is less than the AGC error threshold value, then K is used; otherwise Rev Page AD6654 ⎡ ⎤ SG × 256 ⎢ ⎥ 20 ...
Page 82
... AD6654 format of the AGC error threshold register is four bits to the left of the binary point and eight bits to the right. See the Automatic Gain Control section for details. ⎡ Error Threshold = ⎢ Register Value round ⎢ 20 log ⎣ 10 AGC Average Samples <5:0> This 6-bit register contains the scale used for the CIC filter and the number of power samples to be averaged before being sent to the CIC filter ...
Page 83
... PCLK Master Mode Bit. When the PCLK master mode bit is set, the PCLK pin is configured as an output and the PCLK is driven by the PLL_CLK. Data is transferred out of the AD6654 synchronous to this output clock. When this bit is cleared, the PCLK pin is configured as an input. The user is required to provide a PCLK, and data is transferred out of the AD6654 synchronous to this input clock ...
Page 84
... AD6654 AGC0, I Output <15:0> This read-only register provides the latest in-phase output sample from AGC0. Note that AGC0 might be bypassed, and that AGC0 here is representative of the datapath only. AGC0, Q Output <15:0> This read-only register provides the latest quadrature-phase output sample from AGC0. Note that AGC0 might be bypassed, and that AGC0 here is representative of the datapath only. AGC1, I Output < ...
Page 85
... RC circuit on this pin and maintain a good PLL clock lock. The recommended circuit is given in Figure 76 further recommended that this RC circuit be placed as close as possible to the AD6654 part. This layout consideration ensures that the PLL clock is clean and the PLL lock is closely maintained. ...
Page 86
... AD6654 • In the Intel mode microport, the beginning of a read and write access is indicated by the RDY pin going low. The access is complete only when the RDY pin goes high. In the Motorola mode microport, the completion of a read and write access is indicated by the DTACK pin going low. In both modes and WR ( should be active until access is complete ...
Page 87
... Active Channels Package Description 6 256-Lead CSPBGA (Ball Grid Array) 6 256-Lead CSPBGA (Ball Grid Array) 4 256-Lead CSPBGA (Ball Grid Array) 4 256-Lead CSPBGA (Ball Grid Array) 6 Evaluation Board with AD6654 and Software Rev Page CORNER INDEX AREA ...
Page 88
... AD6654 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05156–0–4/05(0) Rev Page ...