AD6654 Analog Devices, AD6654 Datasheet - Page 10

• Manufacturer Part Number: AD6654
• Description: 14-Bit, 92.16 MSPS, 4 & 6-Channel Wideband IF to Base Band Receiver
• Manufacturer: Analog Devices

Specifications of AD6654

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 92.16MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Adc Architecture: Subranging
• Pkg Type: BGA,CSP

AD6654
MICROPORT TIMING CHARACTERISTICS
Table 8.
Parameter
MICROPORT CLOCK TIMING REQUIREMENTS
INM MODE WRITE TIMING (MODE = 0)
INM MODE READ TIMING (MODE = 0)
MNM MODE WRITE TIMING (MODE = 1)
MNM MODE READ TIMING (MODE = 1)
1
2
3
All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V, and the VDDIO range of 3.0 V to 3.6 V.
C
Specification pertains to control signals: R/ W , (W R ), DS , ( RD ), and CS .
LOAD
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CPUCLK
CPUCLKL
CPUCLKH
SC
HC
SAM
HAM
DRDY
ACC
SC
HC
SAM
HAM
DD
DRDY
ACC
SC
HC
SAM
HAM
DDTACK
ACC
SC
HC
SAM
HAM
DD
DDTACK
ACC
= 40 pF on all outputs, unless otherwise noted.
1, 2
CPUCLK Period
CPUCLK Low Time
CPUCLK High Time
Control
Control
Address/Data to ↑CPUCLK Setup Time
Address/Data to ↑CPUCLK Hold Time
↑CPUCLK to RDY (DTACK) Delay
Write Access Time
Control
Control
Address to ↑CPUCLK Setup Time
Address to ↑CPUCLK Hold Time
↑CPUCLK to Data Delay
↑CPUCLK to RDY (DTACK) Delay
Read Access Time
Control
Control
Address/Data to ↑CPUCLK Setup Time
Address/Data to ↑CPUCLK Hold Time
↑CPUCLK to DTACK (RDY) Delay
Write Access Time
Control
Control
Address to ↑CPUCLK Setup Time
Address to ↑CPUCLK Hold Time
CPUCLK to Data Delay
↑CPUCLK to DTACK (RDY) Delay
Read Access Time
3
3
3
3
3
3
3
3
to ↑CPUCLK Setup Time
to ↑CPUCLK Setup Time
to ↑CPUCLK Hold Time
to ↑CPUCLK Setup Time
to ↑CPUCLK Hold Time
to ↑CPUCLK Setup Time
to ↑CPUCLK Hold Time
to ↑CPUCLK Hold Time
Rev. 0 | Page 10 of 88
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
Min
10.0
1.53
1.70
0.80
0.09
0.76
0.20
3.51
3 × t
4.50
3 × t
1.00
0.00
0.00
0.57
4.10
3 × t
1.00
0.00
0.00
0.57
4.20
3 × t
CPUCLK
CPUCLK
CPUCLK
CPUCLK
Typ
0.5 × t
0.5 × t
1.00
0.03
0.80
0.20
5.0
5.0
CPUCLK
CPUCLK
Max
6.72
9 × t
6.72
9 × t
5.72
9 × t
6.03
9 × t
CPUCLK
CPUCLK
CPUCLK
CPUCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns