AD7829-1 Analog Devices, AD7829-1 Datasheet - Page 17

• Manufacturer Part Number: AD7829-1
• Description: 3 V/5 V, 2 MSPS, 8-Bit, 8-Channel ADC
• Manufacturer: Analog Devices

Specifications of AD7829-1

• Resolution (bits): 8bit
• # Chan: 8
• Sample Rate: 2MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: 2 V p-p,2.5V p-p,Uni 2.0V,Uni 2.5V
• Adc Architecture: Flash
• Pkg Type: SOIC,SOP

PARALLEL INTERFACE
The parallel interface of the AD7829-1 is eight bits wide. Figure 23
shows a timing diagram illustrating the operational sequence of
the AD7829-1 parallel interface. The multiplexer address is latched
into the AD7829-1 on the falling edge of the RD input. The on-
chip track/hold goes into hold mode on the falling edge of
CONVST . A conversion is also initiated at this point. When the
conversion is complete, the end of conversion line ( EOC ) pulses
low to indicate that new data is available in the output register
of the AD7829-1. The EOC pulse stays logic low for a maximum
time of 110 ns.
DB0 TO DB7
A0 TO A2
CONVST
EOC
CS
RD
t
2
t
1
Figure 23. AD7829-1 Parallel Port Timing
Rev. 0 | Page 17 of 20
However, the
RD
interrupt of a microprocessor. CS
the 8-bit conversion result. It is possible to tie CS permanently
low and use only RD to access the data. In systems where the
part is interfaced to a gate array or ASIC, this EOC pulse can be
applied to the CS
AD7829-1 and into the gate array or ASIC. This means that the
gate array or ASIC does not need any conversion status
recognition logic, and it also eliminates the logic required in the
gate array or ASIC to generate the read signal for the AD7829-1.
t
CHANNEL
ADDRESS
t
11
6
NEXT
. This
t
t
4
9
t
12
EOC
t
8
VALID
DATA
EOC
line can be used to drive an edge-triggered
t
13
and
t
t
7
10
t
pulse can be reset high by a rising edge of
5
RD
t
3
inputs to latch data out of the
and
RD
going low accesses
AD7829-1