AD7829-1 Analog Devices, AD7829-1 Datasheet - Page 13

• Manufacturer Part Number: AD7829-1
• Description: 3 V/5 V, 2 MSPS, 8-Bit, 8-Channel ADC
• Manufacturer: Analog Devices

Specifications of AD7829-1

• Resolution (bits): 8bit
• # Chan: 8
• Sample Rate: 2MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: 2 V p-p,2.5V p-p,Uni 2.0V,Uni 2.5V
• Adc Architecture: Flash
• Pkg Type: SOIC,SOP

Capacitor C2 in Figure 13 is typically about 4 pF and can be
primarily attributed to pin capacitance. The resistor, R1, is a
lumped component made up of the on resistance of several
components, including that of the multiplexer and the track-
and-hold. This resistor is typically about 310 Ω. Capacitor C1
is the track-and-hold capacitor and has a capacitance of 0.5 pF.
Switch 1 is the track-and-hold switch, while Switch 2 is that of
the sampling capacitor, as shown in Figure 4 and Figure 5.
When in track phase, Switch 1 is closed and Switch 2 is in
Position A; when in hold mode, Switch 1 opens, while Switch 2
remains in Position A. The track-and-hold remains in hold
mode for 120 ns (see the
which it returns to track mode and the ADC enters its
conversion phase. At this point, Switch 1 opens and Switch 2
moves to Position B. At the end of the conversion, Switch 2
moves back to Position A.
Analog Input Selection
On power-up, the default V
to normal operation from power-down, the V
same one that was selected prior to power-down being initiated.
Table 6 shows the multiplexer address corresponding to each
analog input from V
Table 6.
A2
0
0
0
0
1
1
1
1
Channel selection on the AD7829-1 is made without the
necessity of a write operation. The address of the next channel
to be converted is latched at the start of the current read
operation, that is, on the falling edge of
shown in Figure 14. This allows for improved throughput rates
in “channel hopping” applications.
V
IN
4pF
C2
A1
0
0
1
1
0
0
1
1
Figure 13. Equivalent Analog Input Circuit
V
DD
0
1
0
1
0
1
0
1
A0
D1
D2
IN1
to V
310Ω
Circuit Description section), after
R1
Analog Input Selected
V
V
V
V
V
V
V
V
IN
IN8
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
selection is V
for the AD7829-1.
SW1
0.5pF A
C1
RD
IN1
while
. When returning
SW2
IN
selected is the
B
CS
is low, as
Rev. 0 | Page 13 of 20
DB0 TO DB7
There is a minimum time delay between the falling edge of RD
and the next falling edge of the CONVST signal, t
minimum acquisition time required of the track-and-hold to
maintain 8-bit performance.
performance of the AD7829-1 when channel hopping for
various acquisition times. These results were obtained using an
external reference and internal V
between V
Channel 1.
The on-chip track-and-hold can accommodate input
frequencies to 10 MHz, making the AD7829-1 ideal for
subsampling applications. When the AD7829-1 is converting a
10 MHz input signal at a sampling rate of 2 MSPS, the effective
number of bits typically remains above seven, corresponding to
a signal-to-noise ratio of 42 dB, as shown in
Figure 15. Effective Number of Bits vs. Acquisition Time for the AD7829-1
A0 TO A2
CONVST
TRACK CHx
EOC
RD
CS
8.0
7.5
7.0
6.5
6.0
5.5
5.0
8.5
500
IN1
t
and V
2
HOLD CHx
200
120ns
Figure 14. Channel Hopping Timing
IN4
100
t
1
with 0 V on Channel 4 and 0.5 V on
ACQUISITION TIME (ns)
50
TRACK CHx
Figure 15 shows the typical
40
MID
ADDRESS CHANNEL y
while channel hopping
30
TRACK CHy
VALID
DATA
20
Figure 16.
t
13
AD7829-1
15
t
13
3
. This is the
HOLD CHy
10