AD7367 Analog Devices, AD7367 Datasheet - Page 25

• Manufacturer Part Number: AD7367
• Description: True Bipolar Input, Dual 14-Bit, 2-Channel, Simultaneous Sampling SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7367

• Resolution (bits): 14bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip,SE-Uni
• Ain Range: Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 5.0V,Uni (Vref) x 4,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

Table 13. SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
Setting
RCKFE = 1
LRFS = 1
RFSR = 1
IRFS = 1
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
TFSR = RFSR = 1
Table 14. SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2)
Setting
RXSE = 1
SLEN = 1111
AD7366/AD7367 TO TMS320VC5506
The serial interface on the TMS320VC5506 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices such as the
AD7366/AD7367. The CS input allows easy interfacing between
the TMS320VC5506 and the AD7366/AD7367 without any glue
logic required. The serial ports of the TMS320VC5506 are set
up to operate in burst mode with internal CLKX0 (Tx serial
clock on Serial Port 0) and FSX0 (Tx frame sync from Serial
Port 0). The serial port control (SPC) registers must be set up as
shown in Table 15.
Table 15. Serial Port Control Register Setup
SPC
SPC0
SPC1
The connection diagram is shown in Figure 31. The V
of the AD7366/AD7367 takes the same supply voltage as the
power supply pin of the TMS320VC5506. This allows the ADC
to operate at a higher voltage than its serial interface and,
therefore, the TMS320VC5506, if necessary.
FO
0
0
Description
Secondary side enabled
16-bit data-word (or can be set to 1101 for
14-bit data-word)
Description
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
Internal RFS used
Receive MSB first
Zero fill
Internal receive clock
Receive enabled
16-bit data-word (or can be set to 1101 for
14-bit data-word)
FSM
1
1
MCM
1
0
TXM
1
0
DRIVE
pin
Rev. D | Page 25 of 28
As with the previous interfaces, conversion can be initiated
from the TMS320VC5506 or from an external source, and the
processor is interrupted when the conversion sequence is
completed.
AD7366/AD7367 TO DSP563xx
The connection diagram in Figure 32 shows how the AD7366/
AD7367 can be connected to the enhanced synchronous serial
interface (ESSI) of the DSP563xx family of DSPs from Motorola.
There are two on-board ESSIs, and each is operated in synchro-
nous mode (Bit SYN = 1 in the CRB register) with internally
generated word length frame sync for both Tx and Rx (Bit
FSL1 = 0 and Bit FSL0 = 0 in the CRB register).
Normal operation of the ESSI is selected by setting MOD = 0 in
the CRB register. Set the word length to 16 by setting Bit WL1 = 1
and Bit WL0 = 0 in the CRA register. The FSP bit in the CRB
register should be set to 1 so that the frame sync is negative.
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 31. Interfacing the AD7366/AD7367 to the TMS320VC5506
AD7366/
AD7367*
CNVST
D
D
V
BUSY
SCLK
DRIVE
OUT
OUT
CS
A
B
AD7366/AD7367
CLKX0
CLKR0
CLKX1
CLKR1
DR0
DR1
FSX0
FSR0
FSR1
INTn
XF
TMS320VC5506*
V
DD