AD7367 Analog Devices, AD7367 Datasheet - Page 10

• Manufacturer Part Number: AD7367
• Description: True Bipolar Input, Dual 14-Bit, 2-Channel, Simultaneous Sampling SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7367

• Resolution (bits): 14bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip,SE-Uni
• Ain Range: Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 5.0V,Uni (Vref) x 4,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7366/AD7367
Pin No.
18
19
20
21
22
24
Mnemonic
REFSEL
CS
SCLK
CNVST
BUSY
DGND
Description
Internal/External Reference Selection, Logic Input. If this pin is tied to logic high, the on-chip 2.5 V reference is
used as the reference source for both ADC A and ADC B. In addition, Pin D
decoupling capacitors. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7366/
AD7367 through the D
Chip Select, Active Low Logic Input. This input frames the serial data transfer. When CS is logic low, the output
bus is enabled and the conversion result is output on D
Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7366/AD7367.
Conversion Start, Logic Input. This pin is edge triggered. On the falling edge of this input, the track/hold goes
into hold mode and the conversion is initiated. If CNVST is low at the end of a conversion, the part goes into
power-down mode. In this case, the rising edge of CNVST instructs the part to power up again.
Busy Output. BUSY transitions high when a conversion is started and remains high until the conversion
is complete.
Digital Ground. Ground reference point for all digital circuitry on the AD7366/AD7367. The DGND pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
CAP
A pin, the D
Rev. D | Page 10 of 28
CAP
B pin, or both pins.
OUT
A and D
OUT
B.
CAP
A and Pin D
CAP
B must be tied to