AD7367 Analog Devices, AD7367 Datasheet - Page 21

• Manufacturer Part Number: AD7367
• Description: True Bipolar Input, Dual 14-Bit, 2-Channel, Simultaneous Sampling SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7367

• Resolution (bits): 14bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip,SE-Uni
• Ain Range: Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 5.0V,Uni (Vref) x 4,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

SHUTDOWN MODE
Shutdown mode is intended for use in applications where slow
throughput rates are required. Shutdown mode is suited to
applications where a series of conversions performed at a
relatively high throughput rate are followed by a long period
of inactivity and thus, shutdown. When the AD7366/AD7367
are in full power-down, all analog circuitry is powered down.
The falling edge of CNVST initiates the conversion. The BUSY
output subsequently goes high to indicate that the conversion is
in progress. After the conversion is completed, the BUSY output
returns low. If the CNVST signal is at logic low when BUSY
goes low, the part enters shutdown at the end of the conversion
phase. While the part is in shutdown mode, the digital output
code from the last conversion on each ADC can still be read
from the D
low as described in the Serial Interface section. The D
return to three-state when CS is brought back to logic high.
To exit full power-down and to power up the AD7366/AD7367,
a rising edge of CNVST is required. After the required power-up
time has elapsed, CNVST can be brought low again to initiate
another conversion, as shown in Figure 24 (see the Power-Up
Times section for power-up times associated with the AD7366/
AD7367).
OUT
CNVST
BUSY
SCLK
pins. To read the D
CS
t
OUT
2
data, CS must be brought
t
CONVERT
Figure 24. Autoshutdown Mode for the AD7366
OUT
pins
ENTERS SHUTDOWN
Rev. D | Page 21 of 28
1
t
3
POWER-UP TIMES
The AD7366/AD7367 have one power-down mode, which is
described in detail in the Shutdown Mode section. This section
deals with the power-up time required when coming out of
shutdown mode. It should be noted that the power-up times (as
explained in this section) apply with the recommended capaci-
tors in place on the D
shutdown, CNVST must be brought high and remain high for a
minimum of 70 μs, as shown in Figure 24.
When power supplies are first applied to the AD7366/AD7367,
the ADC can power up with CNVST in either the low or high
logic state. Before attempting a valid conversion, CNVST must
be brought high and remain high for the recommended power-
up time of 70 μs. Then CNVST can be brought low to initiate a
conversion. With the AD7366/AD7367, no dummy conversion
is required before valid data can be read from the
To place the part in shutdown mode when the supplies are first
applied, the AD7366/AD7367 must be powered up and a
conversion initiated. However, CNVST should remain in the
logic low state so that when the BUSY signal goes low, the part
enters shutdown.
When supplies are applied to the AD7366/AD7367, sufficient
time must be allowed for any external reference to power up and
to charge the various reference buffer decoupling capacitors to
their final values.
12
SERIAL READ OPERATION
CAP
A and D
t
POWER-UP
CAP
B pins. To power up from
AD7366/AD7367
D
OUT
pins.