SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 39

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
The line length of the cache is determined by the Len field. The Len field is bits [13:12]
for the DCache and bits [1:0] for the ICache. Table 2-9 shows the line length encoding.
The cache type register values for an ARM926EJ-S processor with the following
configuration are shown in Table 2-10:
•
•
•
•
•
See Cache Lockdown Register c9 on page 2-26 for more details on Format C for cache
lockdown.
Function
Reserved
Ctype
S
Dsize
Copyright © 2001-2003 ARM Limited. All rights reserved.
separate instruction and data caches
DCache size = 8KB, ICache size = 16KB
associativity = 4-way
line length = eight words
caches use write-back, register 7 for cache cleaning, and Format C for cache
lockdown.
Reserved
Size
Assoc
M
Len
Register bits
[31:29]
[28:25]
[24]
[23:22]
[21:18]
[17:15]
[14]
[13:12]
Table 2-10 Example Cache Type Register format
Value
b000
b1110
b1 = Harvard cache
b00
b0100 = 8KB
b010 = 4-way
b0
b10 = 8 words per line (32 bytes)
Len field
b10
Other values
Table 2-9 Line length encoding
Cache line length
8 words (32 bytes)
Reserved
Programmer’s Model
2-11