SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 168

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Coprocessor Interface
8.8
8-12
CPABORT
Coprocessor pipeline
CPINSTR[31:0]
CPDOUT[3:0]
The CPABORT signal being asserted HIGH indicates that an
aborted. CPABORT is asserted in the cycle after the Memory stage of the aborting
LDC/STC instruction. This is shown in Figure 8-9.
CHSDE[1:0]
CHSEX[1:0]
CPDIN[3:0]
nCPMREQ
CPBURST
CPABORT
CLK
Copyright © 2001-2003 ARM Limited. All rights reserved.
LDC/STC
0000
Fetch
Decode
ABSENT
0001
GO
Execute 1
ABSENT
LAST
0000
Figure 8-9 CPBURST and CPABORT timing
Execute 2
Memory 1
Memory 2
Write 1
/
instruction has
ARM DDI0198D
Write 2