SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 163

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.3.1
ARM DDI0198D
Coprocessor pipeline
CPLATECANCEL
Interlocked MCR
CPINSTR[31:0]
CPDOUT[31:0]
CPDIN[31:0]
CHSDE[1:0]
CHSEX[1:0]
nCPMREQ
CPPASS
MCR
MRC
CLK
If the data for an MCR operation is not available inside the ARM9EJ-S core pipeline
during its first Decode cycle, then the ARM9EJ-S core pipeline interlocks for one or
more cycles until the data is available. An example of this is where the register being
transferred is the destination from a preceding LDR instruction. In this situation the
MCR instruction enters the Decode stage of the coprocessor pipeline, and remains there
for a number of cycles before entering the Execute stage.
Figure 8-5 shows an example of an interlocked MCR.
MCR/MRC
Copyright © 2001-2003 ARM Limited. All rights reserved.
Fetch
(interlock)
Decode
WAIT
Decode
WAIT
Execute
(WAIT)
LAST
Execute
(LAST)
Ignored
Figure 8-5 Interlocked MCR
Coproc data
Memory
Coprocessor Interface
Write
8-7