SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 111

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Tightly-Coupled Memory Interface
memory. The TCM interface contains a two entry write buffer, which avoids the need
for stall cycles because of the mismatch between the ARM9EJ-S native memory
interface, and the requirements for standard SRAM.
TCM accesses can be extended by using the IRWAIT/DRWAIT inputs to generate wait
states. However, the timing of these and other interface signals is such that the types of
memory sub-systems that can be implemented are limited. For example schemes that
require an address decode to determine if a wait-state should be inserted are not possible
if operating at maximum frequency.
DMA access can be performed either by using the IRWAIT/DRWAIT signals to insert
wait states during a DMA access, or by using the dedicated DMA interface, which
avoids the need to externally multiplex critical interface signals when single cycle
access memory is used.
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
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