SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 3

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Contents
ARM926EJ-S Technical Reference Manual
ARM DDI0198D
Chapter 1
Chapter 2
Chapter 3
Preface
Introduction
1.1
Programmer’s Model
2.1
2.2
2.3
Memory Management Unit
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Copyright © 2001-2003 ARM Limited. All rights reserved.
About this manual ........................................................................................ xvi
Feedback ..................................................................................................... xxi
About the ARM926EJ-S processor ............................................................. 1-2
About the programmer’s model ................................................................... 2-2
Summary of ARM926EJ-S system control coprocessor (CP15) registers .. 2-3
Register descriptions .................................................................................. 2-7
About the MMU ........................................................................................... 3-2
Address translation ..................................................................................... 3-5
MMU faults and CPU aborts ..................................................................... 3-21
Domain access control .............................................................................. 3-24
Fault checking sequence .......................................................................... 3-26
External aborts .......................................................................................... 3-29
TLB structure ............................................................................................ 3-31
iii