SC16C852VIET,157 NXP Semiconductors, SC16C852VIET,157 Datasheet - Page 32

• Manufacturer Part Number: SC16C852VIET,157
• Description: IC UART DUAL W/FIFO 36TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852VIET,157

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4019; 935282518157; SC16C852VIET; SC16C852VIET

NXP Semiconductors
SC16C852V
Product data sheet
7.10 Scratchpad Register (SPR)
7.12 Transmit FIFO Level Count (TXLVLCNT)
7.13 Receive FIFO Level Count (RXLVLCNT)
7.11 Division Latch (DLL and DLM)
7.9 Extra Feature Control Register (EFCR)
This is a write-only register, and it allows the software access to these registers:
First Extra Register Set, Second Extra Register Set, Transmit FIFO Level Counter
(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).
Table 24.
Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can
only be accessed if EFCR[2:1] are zeroes.
The SC16C852V provides a temporary data register to store 8 bits of user information.
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
This register is a read-only register. It reports the fill level of the receive FIFO (the number
of characters in the RXFIFO).
Bit
7:3
2:1
0
Symbol
EFCR[7:3]
EFCR[2:1]
EFCR[0]
Extra Feature Control Register bits description
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
reserved
Enable Extra Feature Control bits
Enable TXLVLCNT and RXLVLCNT access
Description
Rev. 5 — 21 January 2011
00 = General Register Set is accessible
01 = First Extra Register Set is accessible
10 = Second Extra Register Set is accessible
11 = reserved
0 = TXLVLCNT and RXLVLCNT are disabled
1 = TXLVLCNT and RXLVLCNT are enabled and can be read
SC16C852V
© NXP B.V. 2011. All rights reserved.
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