SC16C852VIET,157 NXP Semiconductors, SC16C852VIET,157 Datasheet - Page 26

• Manufacturer Part Number: SC16C852VIET,157
• Description: IC UART DUAL W/FIFO 36TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852VIET,157

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4019; 935282518157; SC16C852VIET; SC16C852VIET

NXP Semiconductors
SC16C852V
Product data sheet
Table 11.
[1]
[2]
Table 12.
[1]
Table 13.
[1]
Bit
3
(cont.)
2
1
0
FCR[7]
0
0
1
1
FCR[5]
0
0
1
1
For 128-byte FIFO mode, refer to
For 128-byte FIFO mode, refer to
When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see
When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see
Symbol
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
RCVR trigger levels
TX FIFO trigger levels
FCR[6]
0
1
0
1
FCR[4]
0
1
0
1
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Description
Transmit operation in mode ‘1’: When the SC16C852V is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY signal will be a logic 1 when
the transmit FIFO is completely full, see
be a logic 0 when the trigger level has been reached.
Receive operation in mode ‘1’: When the SC16C852V is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the RXRDY signal will go to a logic 0.
Once activated, it will go to a logic 1 after there are no more characters in the
FIFO.
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
Rev. 5 — 21 January 2011
RX FIFO trigger level in 32-byte FIFO mode
8 bytes
16 bytes
24 bytes
28 bytes
TX FIFO trigger level in 32-byte FIFO mode
16 bytes
8 bytes
24 bytes
30 bytes
Section
Section
7.16,
7.15,
Section
Section
…continued
7.17,
7.17,
Section 6.4 “FIFO
Section 6.4 “FIFO
Section
Section
Section 6.10 “DMA
7.18.
7.18.
SC16C852V
operation”.
operation”.
[1]
[1]
© NXP B.V. 2011. All rights reserved.
operation”. It will
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