SC16C852VIET,157 NXP Semiconductors, SC16C852VIET,157 Datasheet - Page 25

• Manufacturer Part Number: SC16C852VIET,157
• Description: IC UART DUAL W/FIFO 36TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852VIET,157

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4019; 935282518157; SC16C852VIET; SC16C852VIET

NXP Semiconductors
SC16C852V
Product data sheet
7.3.1.1 Mode 0 (FCR bit 3 = 0)
7.3.1.2 Mode 1 (FCR bit 3 = 1)
7.3.1 DMA mode
7.3.2 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
In this mode, Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR, if
FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the
Receive Holding Register (RHR) is loaded with a character.
In this mode, the transmit ready (TXRDY) is set when the transmit FIFO is below the
programmed trigger level. The receive ready (RXRDY) is set when the receive FIFO fills
to the programmed trigger level. However, the FIFO continues to fill regardless of the
programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill
level is above the programmed trigger level.
Table 11.
Bit
7:6
5:4
3
Symbol
FCR[7:6]
FCR[5:4]
FCR[3]
FIFO Control Register bits description
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Description
Receive trigger level in 32-byte FIFO mode.
These bits are used to set the trigger level for receive FIFO interrupt and flow
control. The SC16C852V will issue a receive ready interrupt when the
number of characters in the receive FIFO reaches the selected trigger level.
Refer to
Transmit trigger level in 32-byte FIFO mode.
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C852V will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table
DMA mode select.
Transmit operation in mode ‘0’: When the SC16C852V is in the non-FIFO
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO, the TXRDY signal will be a logic 0. Once
active, the TXRDY signal will go to a logic 1 after the first character is loaded
into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C852V is in non-FIFO
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is
at least one character in the receive FIFO, the RXRDY signal will be a
logic 0. Once active, the RXRDY signal will go to a logic 1 when there are no
more characters in the receiver.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Rev. 5 — 21 January 2011
13.
Table
12.
[1]
[2]
SC16C852V
© NXP B.V. 2011. All rights reserved.
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