SC16IS740IPW,112 NXP Semiconductors, SC16IS740IPW,112 Datasheet - Page 26

• Manufacturer Part Number: SC16IS740IPW,112
• Description: IC UART SINGLE W/FIFO 16-TSSOP
• Manufacturer: NXP Semiconductors
• Type: UART with 64-byte FIFOs and IrDA encoder/decoderr

Specifications of SC16IS740IPW,112

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3648-5; 935280988112; SC16IS740IPW

NXP Semiconductors
SC16IS740_750_760_6
Product data sheet
8.5 Line Status Register (LSR)
Table 16
Table 16.
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.
Bit
7
6
5
4
3
2
1
0
Symbol
LSR[7]
LSR[6]
LSR[5]
LSR[4]
LSR[3]
LSR[2]
LSR[1]
LSR[0]
shows the Line Status Register bit settings.
Line Status Register bits description
Description
FIFO data error.
THR and TSR empty. This bit is the Transmit Empty indicator.
THR empty. This bit is the Transmit Holding Register Empty indicator.
break interrupt
framing error
parity error.
overrun error
data in receiver
Single UART with I
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO.
logic 0 = transmitter hold and shift registers are not empty
logic 1 = transmitter hold and shift registers are empty
logic 0 = transmit hold register is not empty
logic 1 = transmit hold register is empty. The host can now load up to
64 characters of data into the THR if the TX FIFO is enabled.
logic 0 = no break condition (normal default condition)
logic 1 = a break condition occurred and associated character is 0x00, that
is, RX was LOW for one character time frame
logic 0 = no framing error in data being read from RX FIFO (normal default
condition).
logic 1 = framing error occurred in data being read from RX FIFO, that is,
received data did not have a valid stop bit
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from RX FIFO
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the RX FIFO
Rev. 06 — 13 May 2008
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
SC16IS740/750/760
© NXP B.V. 2008. All rights reserved.
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