SC16IS740IPW,112 NXP Semiconductors, SC16IS740IPW,112 Datasheet - Page 14

• Manufacturer Part Number: SC16IS740IPW,112
• Description: IC UART SINGLE W/FIFO 16-TSSOP
• Manufacturer: NXP Semiconductors
• Type: UART with 64-byte FIFOs and IrDA encoder/decoderr

Specifications of SC16IS740IPW,112

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3648-5; 935280988112; SC16IS740IPW

NXP Semiconductors
SC16IS740_750_760_6
Product data sheet
7.4 Hardware reset, Power-On Reset (POR) and software reset
These three reset methods are identical and will reset the internal registers as indicated in
Table
Table 4
Table 4.
[1]
[2]
[3]
Table 5
Table 5.
Register
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Enhanced Feature Register
Receiver Holding Register
Transmitter Holding Register
Transmission Control Register
Trigger Level Register
Transmit FIFO level
Receive FIFO level
I/O direction
I/O interrupt enable
I/O control
Extra Feature Register
Signal
TX
RTS
I/Os
IRQ
Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal
RESET, POR or Software Reset, that is, they hold their initialization values during reset.
This register is not supported in SC16IS740.
Only UART Software Reset bit is supported in this register.
4.
summarizes the state of register.
summarizes the state of registers after reset.
[3]
Register reset
Output signals after reset
[2]
Reset state
HIGH
HIGH
inputs
HIGH by external pull-up
[2]
Single UART with I
Rev. 06 — 13 May 2008
[1]
Reset state
all bits cleared
bit 0 is set; all other bits cleared
all bits cleared
reset to 0001 1101 (0x1D)
all bits cleared
bit 5 and bit 6 set; all other bits cleared
bits 0:3 cleared; bits 4:7 input signals
all bits cleared
pointer logic cleared
pointer logic cleared
all bits cleared.
all bits cleared.
reset to 0100 0000 (0x40)
all bits cleared
all bits cleared
all bits cleared
all bits cleared
all bits cleared
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
SC16IS740/750/760
© NXP B.V. 2008. All rights reserved.
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