CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 67

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Table 2-1. Hardware Signal Definitions (4 of 6)
28237-DSH-001-C
RxCLK
UTOPIA1
PADDR[12:0]
PCS*
PAS*
PWNR
PDS*
PCLK
PDATA [7:0]
PINT*
PRST*
PWAIT*
Pin Label
Framer Control/Clock
UTOPIA level select
PHY Address
ATM PHY Chip Select
Address Strobe
Write/Not Read
Data/Address Strobe
PHY Bus CLK
PHY Data Bus
Interrupt Input
Reset Output
PHY Interface Wait
Signal Name
Mindspeed Technologies
I/O
I/O
O
O
O
O
O
O
O
I
I
I
I
(1)
UTOPIA receive clock.
Selects level 1/level 2 operation. In level 1 mode, address
pins are forced to be outputs independent of master/slave
mode. When UTOPIA1 input is a logic high, the UTOPIA
address signals, TxADDR[4:0] and RxADDR[4:0], are
forced as outputs. This pin must be pulled high or low.
Address bus to PHY device.
The PCS* is connected to the chip select input of the
Mindspeed PHY device.
PAS* is used to drive the AS* pin of the Mindspeed PHY
device.
This output provides the same function for the Mindspeed
PHY device. Logic 1 writes; logic 0 reads.
PHY device data strobe.
Interface clock to PHY device.
PHY Device Data Bus.
PHY device interrupt signal.
Asserted by the CN8237 whenever the HRST* input is
asserted.
Externally generated signal to extend PHY device
accesses.
™
2.10 Logic Diagram and Pin Descriptions
Definition
2.0 Architecture Overview
2-33