CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 289

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
13.10.1 Head of Line Flushing (HoLF)
28237-DSH-001-C
to the transmit ATM UTOPIA interface unit, with cell delineation pulses at the
starting byte of every cell. Only complete 53-byte cells are supplied to the ATM
UTOPIA interface. If the transmit cell FIFO buffer is empty, the transmit cell
synchronization logic indicates that no more data can be transferred to the framer.
If the SAR is set up as a UTOPIA Master in multi-PHY operations, the PHY
device indicates that it can receive another cell by asserting its UTOPIA CLAV
signal. Cells are then transmitted to the PHY device. The UTOPIA Master waits
until it receives the CLAV signal from the PHY device, and therefore blocks the
transmission of all other cells in the transmit FIFO. If this PHY device stops
working, all other PHY devices are blocked. This is called head of the line
blocking.
Line Flushing (HoLF) mechanism flushes the blocking cell out of the transmit
FIFO. To enable this mechanism, set the TX_FIFO_FLUSH_EN bit to a one in
the CONFIG1 register.
reset to 0, and increased based on the UTOPIA TX_CLK. Once the counter
reaches the values TX_CNTR set by the user in the CSR register, the cell is
discarded, and the bit corresponding to the blocking PHY device is set in the
TX_PORT_STATUS register. The counter is reset automatically. If any of the
eight bits in the corresponding mask bit EN_TX_DISCARD in HOST_IMASK1
is set, an interrupt is generated. The TX_DISCARD is cleared once the
TX_STATUS register is read by the host.
NOTE:
cells belonging to this port are discarded or flushed. Ports are disabled by setting
the corresponding bit in the TX_PORT_CTRL register. If a port x is disabled and
a cell pertaining to port x is discarded, bit x in TX_STATUS is not set, and
therefore no interrupt is generated.
65,535 is recommended. For specific DSL applications with variable rate PHY
devices, a value between 50 and 100 is suggested.
The transmit cell synchronization logic supplies a continuous stream of octets
In order to avoid head of the line blocking in the transmit FIFO, a Head of
When the UTOPIA Master puts out the address of a PHY device, a counter is
If the user decides to disable a specific port on the UTOPIA interface, then all
For fault tolerant multi-PHY operations, a maximum TX _CNTR value of
The cell discard does not disable the port.
Mindspeed Technologies
™
13.10 Transmit Cell Synchronization Logic
13.0 ATM UTOPIA Interface
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